Multi-module Memory Research Articles

Reconfigurable Modular Computing System

Purpose of research. A reconfigurable computer system consists of a computing system and special-purpose computers that are used to solve the tasks of vector and matrix algebra, pattern recognition. There are distinctions between matrix and associative systems, neural networks. Matrix computing systems comprise a set of processor units connected through a switching device with multi-module memory. They are designed to solve vector, matrix and data array problems. Associative systems contain a large number of operating devices that can simultaneously process multiple data streams. Neural networks and neurocomputers have high performance when solving problems of expert systems, pattern recognition due to parallel processing of a neural network.Methods. An information graph of the computational process of a reconfigurable modular system was plotted. Structural and functional schemes, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words were developed. Software for modelling the operation of the arithmetic-symbol processor, specialized computing modules, and switching systems was developed.Results. A block diagram of a reconfigurable computing modular system was developed. The system consists of compatible functional modules and is capable of static and dynamic reconfiguration, has a parallel connection structure of the processor and computing modules through the use of interface channels. It consists of an arithmeticsymbol processor, specialized computing modules and switching systems; it performs specific tasks of symbolic information processing, arithmetic and logical operations.Conclusion. Systems with a reconfigurable structure are high-performance and highly reliable computing systems that consist of integrated processors in multi-machine and multiprocessor systems. Reconfigurability of the structure provides high system performance due to its adaptation to computational processes and the composition of the processed tasks.

Variable assignment and instruction scheduling for processor with multi-module memory

Multi-module memory has been employed in high-end digital signal processing system (DSP). It provides high memory bandwidth and low power operating mode for energy savings. However, making full use of these architectural features is a challenging problem for code optimization. In this paper, we propose an integer linear programming (ILP) model to optimize the performance and energy consumption of multi-module memories by solving variable assignment, instruction scheduling and operating mode setting problems simultaneously. The combined effect of performance and energy saving requirements has been considered as well. Specially, we develop two optimization techniques to improve the computation efficiency of our ILP model. The experimental results show that the optimal performance and energy solution can be achieved within a reasonable amount of time.

CROSSTALK AND DISCONTINUITIES REDUCTION ON MULTI-MODULE MEMORY BUS BY PARTICLE SWARM OPTIMIZATION

Due to high-density routing under the CPU and DIMM areas, the original design of even and odd mode characteristic impedances changes. The occurrence of multi-drop problem between the CPU and memory chip causes over- and under-driven that reduce the eye opening. Furthermore, the difierent phase velocities of even- and odd-modes cause timing jitter at the receiver end. This paper proposes two steps to solve the complex issue of signal integrity for the multi-module memory bus. First, particle swarm optimization (PSO) is used to tune the characteristic impedance of the transmission line and on-die termination (ODT) values to improve transmission line impedance changes to obtain maximum power delivery. The fltness function of the algorithm is deflned by selecting the minimum re∞ection coe-cient at the driver side and maximum the transmission coe-cient at the receiver side to reduce the over- and under-driven Second, the timing jitter can be reduced by placing a capacitor to compensate for the velocity difierence caused by difierent propagation modes. Finally, signal integrity enhancements for the DDR3 are verifled by measuring S parameters in the frequency domain and postprocessed eye diagrams in the time domain.

Small World Structure Inspired Many to Many Kernel Associative Memory Models and Their Application

Kernel method is an effective and popular trick in machine learning, and small world network is a common phenomenon which exists widely in social fields. In this paper, by introducing them into Hattori et al's multi-module associative memory for many-to-many associations ((MMA) 2 ), a unified framework of small world structure inspired many-to-many kernel associative memory models (SWSI-M 2 KAMs) is proposed. The SWSI-M 2 KAMs not only can store patterns online without more iteration steps, but also extend the range of the processed intelligent information. More importantly, the SWSI-M 2 KAMs framework can develop more new many-to-many associative memory models by selecting different kernel functions and reduce models' configuration complexity by using the sparse small world architecture. Finally, computer simulations demonstrate that the constructed models have good performance on many-to-many associative memory.

Conflict-free access for streams in multimodule memories

Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access for streams with constant stride. However, this is achieved only for some strides. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to a stream of fixed length. This stream is then stored in a local memory and used in subsequent instructions. This mode of operation is suitable for vector processors and for processors with decoupled access. The scheme and mode of operation proposed produce the largest possible number of conflict-free strides. Memory systems with any ratio between the number of memory modules and memory latency are considered. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Distributed loop network with minimum transmission delay

Distributed loop networks are networks with at least one ring structure. They are widely used in the design of local area networks, multimodule memory organizations, data alignments in parallel memory systems, and supercomputer architecture. In this paper, we give a systematic and unified method of solutions in the design and implementation of these networks. We show that doubly linked loop networks with transmission delay less than or equal to (1+ ε)√3 N can be constructed asymptotically for sufficiently large N, the number of nodes in the network. This is close to the optimal value within a number which is small as compared to N. We then give several infinite classes of values of N for which optimal doubly linked loop networks can be actually designed. The method is then generalized to obtain a new upper bound for possible transmission delays in multiply linked loop networks. Routing and rerouting algorithms are designed for the optimal loop networks.

Increasing the number of strides for conflict-free vector access

Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. Both matched and unmatched memories are considered: we show that the number of strides is even larger for the latter case. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order.

A combinatorial problem related to distributed loop networks

AbstractThe problem under consideration arises from studies on local networks and multimodule memory organizations. The ring network has been one of the popular network topologies used in the design and implementation of local area networks and other configurations. We consider here a generalization of the ring network by adding two fixed‐step links to each node. The resulting networks have low diameter, easy routing, and switching structure and therefore are suitable for implementation in the design of reliable networks. Let N denote the number of nodes in the network. For a given N, we are concerned with the problem of determining the best topologies to minimize the diameter (and, hence, the transmission delay) of the network. We obtain new classes of values of N for which topologies can be found that achieve the lower bound lb = [(√2N ‐ 1 ‐ 1)/2] for the minimum diameter. We also show that for some infinite classes of N this lower bound lb is not achievable.

A Combinatorial Problem Related to Multimodule Memory Organizations

This paper deals with a combinatorial minimization problem arising from studies on multimodule memory organizations. Instead of searching for an optimum solution, a particular solution is proposed and it is demonstrated that it is close to optimum. Lower bounds for the objective functions are obtained and compared with the corresponding values of the particular solution. The maximum percentage deviation of this solution from optimum is also established.

The Organization of High-Speed Memory for Parallel Block Transfer of Data

This paper describes the organization of a multi-module memory, designed to facilitate parallel block transfers. All modules are assumed to be identical, and the individual modules can fetch or store no more than one word or word group during any single memory cycle. Parallel block transfers are made possible in multimodule memories by utilizing a device called the memory circulator and by organizing the memory in a particular way. The memory circulator consists of a bank of interconnected registers, one for each memory, and control circuitry. The memory system is organized so that ascending logical addresses are distributed cyclically among the modules. If there are 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> modules, then any individual word is accessed by using the least significant b bits of a memory address to select a module and by using the remaining bits to select an address within a module. The memory circulator can load and store a contiguous block of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> words by selecting all modules and broadcasting a single address to all modules. A contiguous block can be displaced in memory by a multiple of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> words by broadcasting different load and store addresses for a block of data. The circulator control circuitry includes a masking capability so that blocks smaller than 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> can be moved in this fashion. When the displacement of a block transfer is not a multiple of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> a physical circulation of the data in the memory circulator registers is required.