The Organization of High-Speed Memory for Parallel Block Transfer of Data

Abstract

This paper describes the organization of a multi-module memory, designed to facilitate parallel block transfers. All modules are assumed to be identical, and the individual modules can fetch or store no more than one word or word group during any single memory cycle. Parallel block transfers are made possible in multimodule memories by utilizing a device called the memory circulator and by organizing the memory in a particular way. The memory circulator consists of a bank of interconnected registers, one for each memory, and control circuitry. The memory system is organized so that ascending logical addresses are distributed cyclically among the modules. If there are 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> modules, then any individual word is accessed by using the least significant b bits of a memory address to select a module and by using the remaining bits to select an address within a module. The memory circulator can load and store a contiguous block of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> words by selecting all modules and broadcasting a single address to all modules. A contiguous block can be displaced in memory by a multiple of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> words by broadcasting different load and store addresses for a block of data. The circulator control circuitry includes a masking capability so that blocks smaller than 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> can be moved in this fashion. When the displacement of a block transfer is not a multiple of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sup> a physical circulation of the data in the memory circulator registers is required.