Multilayer Circuit Research Articles

Cold Sintering Na2Mo2O7 Ceramic with Poly(ether imide) (PEI) Polymer to Realize High-Performance Composites and Integrated Multilayer Circuits

The cold-sintering process is utilized to fabricate ceramic–polymer (Na2Mo2O7-poly(ether imide), PEI) composites and integrated multilayer circuits. The Na2Mo2O7-PEI bulk composites cold-sintered at 120 °C show high densities (>90% theoretical). The permittivity at microwave frequencies decreases with increasing PEI content, following the classical logarithmic mixing law, and Qf values show no deterioration with the addition of PEI. Furthermore, the characteristic dielectric breakdown strength of the ceramic–polymer composite obtained from a Weibull plot increases dramatically from 55.1 to 107.5 MV/m with 10–20 vol % PEI additions. In the case of high PEI content where there is more segregation of the polymer within the ceramic matrix, there is a gradual decrease in the dielectric breakdown strength. Na2Mo2O7-PEI-Ag bulk ring resonators can be obtained by post screen printing, and the mixing laws are used to calculate the permittivity of the ring resonators. As a prototype of integrated multilayer circuit...

Engineering orthogonal synthetic timer circuits based on extracytoplasmic function σ factors

The rational design of synthetic regulatory circuits critically hinges on the availability of orthogonal and well-characterized building blocks. Here, we focus on extracytoplasmic function (ECF) σ factors, which are the largest group of alternative σ factors and hold extensive potential as synthetic orthogonal regulators. By assembling multiple ECF σ factors into regulatory cascades of varying length, we benchmark the scalability of the approach, showing that these ‘autonomous timer circuits’ feature a tuneable time delay between inducer addition and target gene activation. The implementation of similar timers in Escherichia coli and Bacillus subtilis shows strikingly convergent circuit behavior, which can be rationalized by a computational model. These findings not only reveal ECF σ factors as powerful building blocks for a rational, multi-layered circuit design, but also suggest that ECF σ factors are universally applicable as orthogonal regulators in a variety of bacterial species.

Hermetic Broadband 3-dB Power Divider/Combiner in Substrate-Integrated Waveguide (SIW) Technology

A dual-layer 3-dB substrate-integrated waveguide power divider/combiner is designed, fabricated, and tested. Very good input and output matching as well as high isolation are exhibited over a measured 50% fractional bandwidth when a 10-dB reference level is considered. A completely shielded design significantly reduces insertion losses when compared to the majority of other state-of-the-art architectures. This device can be integrated with multilayer planar circuits, and it is fully compatible with the standard printed-circuit board technology.

3-D Multilayer S-Bend Silicon Waveguide Optical Interconnect

A 3-D S-bend silicon waveguide optical interconnect on silicon on insulator is proposed to connect optical circuits in a multilayered photonic-integrated circuit (PIC). Critical parameters like bending loss, axial shift, and coupling loss are calculated for efficient implementation in the dense wavelength division multiplexing wavelength spectrum (1.46-1.62 μm). The critical parameters for tight bends are kept in control by optimizing geometrical parameters for application in miniaturized optical circuits in multilayered PIC. Possibility of fabrication of proposed complex interconnect is also explored.

Mathematical Modeling of a Linear-Induction Motor Based on Detailed Equivalent Circuits

Electric drives based on traction linear-induction motors are used in industry and city transport. The main advantages of this electric drive are unrestricted acceleration and vehicle climbing angles, as well as ecological cleanliness. The development of high-speed design and analysis software tools for linear electric motors is thus becoming quite timely. The use of the finite-element method for solving field problems in a three-dimensional setting and dynamic vehicle-operation regimes is time-consuming. It is proposed to use a detailed magnetic equivalent circuit of a linear-induction-motor longitudinal section with the introduction of the Bolton coefficient to correct for the transverse-edge effect in a solid secondary element. Model features based on multilayer magnetic equivalent circuits are shown, and the effect of the number of layers on the designed motor-traction force is evaluated. When selecting an appropriate pole pitch-to motor gap ratio, a two-level equivalent circuit turns out to be suitable. The secondary element is represented in the model as a set of rectangular rods connected in parallel. The influence of the calculation method of the secondary rods’ motional EMF on the motor-traction-force accuracy is shown. The greatest error is observed in a low-slip region (when the motor passes into a generative braking regime) and the simplest spatial derivative of the magnetic flux. When the derivative calculation formula becomes more complicated, the indicated error sharply decreases. Another way to reduce the calculation error of the motional EMF in the secondary element circuit is to increase the number of these circuits by decreasing the width of the elementary rod. The prominence of the detailed magnetic equivalent-circuit method and convenience of online viewing should be noted.

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.

Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing.

The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag) nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations.

A New Printed Electronics Approach Eliminating Redundant Fabrication Process of Vertical Interconnect Accesses: Building Multilayered Circuits in Porous Materials

AbstractPrinted electronics are striving for smaller size, increased functionality, and lower energy consumption, which impose critical demand for multilayered printed circuits. As a low‐cost and green substrate, cellulose paper has become the most attractive choice for the printing of sustainable and disposable electronics. However, the redundant processes of drilling holes and/or depositing of dielectric materials, when fabricating the vertical interconnect access (VIA) for these multilayered circuits, greatly increase the cost. In this paper, a simple, cost‐effective, and scalable method is proposed for fabricating high‐performance, multilayered paper‐based circuits which contain highly conductive VIAs without physically drilling holes or depositing additional dielectric material. Taking advantages of inkjet printing and electroless copper deposition, the metallization depth of the substrate can be controlled with ease. In the proposed method, the porous structure of cellulose paper, which is previously an obstacle to printed electronics, becomes an advantage by triggering the 3D copper deposition, resulting in an ultralow sheet resistance of ≈4.8 mΩ sq−1 for single layer traces and ≈2.6 mΩ sq−1 for VIAs. A functional double‐layered and battery‐free device with drill‐less VIA, featuring an energy harvesting function, is fabricated using the proposed method on paper for the first time.

Multilayer Substrate Integrated Waveguide Six-Port Circuit

In this paper a new design of a six-port circuit based on multilayer substrate integrated waveguides (SIW) is presented. This design is based on the use of a multilayer structure aimed at reducing the dimension of the circuit while conserving the performances of the component. The designed SIW six-port is composed of two basic elements, a SIW power divider and directional coupler. These two elements are designed, optimized and matched to produce a better performance at the required operating frequency of 11 GHz. The results of simulations show that the new multilayer SIW six-port circuit has good performances including a good return loss and isolation under–20 dB and the transmission magnitude better than–10 dB. This multilayer SIW six-port has the advantage of a small size 160-34.8 mm; its width is about 50% smaller than the planar SIW six-port circuit, which helps to get a higher density of integration in telecommunication systems and allows much smaller devices to be conceived.A microstrip toSIWtransition is used in order to facilitate the integration of this component into other planar circuits. The structures are designed, simulated and optimized using the Ansoft HFSS simulation software.

A Review on the Application of RNA based Nanotechnology in In Vivo Computation

Computing in molecular-scale has been explored from the era of pre genomics with a limitation in Moore's law for devices based on silicon. The development of in vivo computation requires low energy consumption in molecularscale. The concept of DNA computing has rationalized the basic Boolean functions into multi-layered circuits. In the Recent year, the concept of RNA nanotechnology has emerged as an alternative approach because the RNA nanoparticles are emerging as a promising medium for a nanodevice with a platform for computing in molecularscale. In RNA computing, the varieties of small RNA sequences can work antagonistically to carry out computational logic in circuits to execute the process of in vivo computation. Though RNA computation is promising in most cases, but it is still in the infant stage and there are many challenges to collaborations between the people in RNA nanotechnology and computer science to carry out the necessary advancement in performing in vivo computation by RNA Nanotechnology.

Определение эффективных параметров теплоотводящих слоев в многослойных печатных платах

Определение эффективных параметров теплоотводящих слоев в многослойных печатных платах

3D-принтер DragonFly – революционное решение для изготовления многослойных печатных плат

3D-принтер DragonFly – революционное решение для изготовления многослойных печатных плат

Multilayer Distributed Circuit Modeling for Galvanic Coupling Intrabody Communication

Characterization of the human body as a transmission medium for electrical signals is a necessity for using intrabody communication (IBC) technique into connecting wearable electronic sensors and devices. In this paper, we propose a novel multilayer distributed circuit model for galvanic-coupling type IBC, which is emphasized on the propagation characteristics in contrast with other IBC models. Based on the model, a program is written in MATLAB to investigate the propagation characteristics of a human body channel with the frequency of 10 MHz to 20 MHz and the distance of 5 cm to 10 cm. Finally, a galvanic coupling IBC measurement is implemented to verify the proposed model. The outcome proves that the model is valid and correct.

Design of slime-mold-inspired multi-layered single-electron circuit

ABSTRACTWe propose a new single-electron circuit (SEC) that mimics the behaviours of slime molds. The SEC has unique properties and many advantages including extremely low power consumption. However, the most appropriate information processing way on the SEC has not been established yet. As one approach to find the suitable way, we focus on a natural phenomenon, specifically, the behaviours of slime molds. These molds can feed efficiently and their behaviours can be regarded as performing information processing. Their information-processing-like behaviours can be divided into three functions. Therefore, if we can express these functions on the circuit, it can mimic the slime mold behaviour, i.e. it can operate as a slime-mold-inspired information-processing circuit. In this study, we designed a slime-mold-inspired SEC that utilised three functions based on three types of behaviours, and attempted to imitate these functions by using a multi-layered structure. Our circuit has four layers; three for mimicking the divided functions and the last for output. We evaluated its operation by Monte Carlo simulation and confirmed its operation was correct.This paper indicates design of a new single-electron circuit (SEC). For the SEC to process information efficiently, we focus on the behaviors of slime molds. It is known that these molds can feed efficiently and their behaviors can be regarded as performing information processing. In this study, we designed a slime-mold-inspired SEC having a multi-layered structure. We evaluated its operation by Monte Carlo simulation and confirmed its operation was correct. Figure shows a sample operation of our circuit. (a) is the input pattern and (b) is the output pattern, respectively. The optimal path was revealed.

A graph-theoretic framework for analyzing the speeds and efficiencies of battery pack equalization circuits

This article presents a framework for analyzing the speeds and efficiencies of different battery pack balancing circuits. The article is motivated by the growing need for fast and efficient charge balancing in lithium-ion battery packs. There is an excellent literature on the design of different balancing circuits, including both single- and multi-layer active and passive topologies. However, this literature lacks a formal framework for representing different balancing circuits in a compact manner conducive to quantitative analysis. We address this challenge by representing the balancing pathways between different cells in a battery pack using a directed graph. This makes it possible to systematically analyze: (i) the “completeness” of a balancing circuit (the ability to address the imbalance between any two cells directly, even if they are not adjacent); (ii) the shortest path for balancing any two given cells; and (iii) the average efficiency of a balancing circuit for a statistical distribution of imbalance scenarios. The proposed framework is flexible: it can represent both single-layer and multi-layer balancing circuits, including circuits with multiple distinct types of converters. We demonstrate the capabilities of this framework through an example study involving the comparison of multiple balancing circuits for a 16-cell lithium-ion battery pack.

Predicting delamination in multilayer composite circuit boards with bonded microelectronic components

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of bending test specimens consisting of PCB substrates bonded with the underfill adhesive. The model provided relatively accurate predictions of the crack paths and the bending strength of the actual underfilled BGA-PCB assemblies for a range of adhesive fillet sizes, PCB stiffnesses, and strain rates.

Three dimensional printed electronic devices realised by selective laser melting of copper/high-density-polyethylene powder mixtures

A manufacturing process with the capability to integrate electronics into 3D structures is of great importance to the development of next-generation miniaturised devices. In this study, Selective Laser Melting (SLM) was used to process copper/high-density-polyethylene (HDPE) powder mixtures to build conductive tracks in a 3D circuit system. The effects of copper/HDPE volume ratio, laser input power and scanning speed on the resistivity of CO2 laser processed tracks were investigated. The resistivity of the tracks decreased from 26.6±0.6×10−4Ωcm to 1.9±0.1×10−4Ωcm as the copper volume ratio increased from 30% to 60%. However, further increasing the copper ratio to 100% resulted in poor conductivity. The lowest resistivity was achieved with an input power of 20W and scanning speed of 80mm/s. Additionally, processing using single-track-scanning and raster-scanning programs was compared; the overall energy distribution on the surface was more uniform using a raster-scanning program, which further reduced the resistivity to 0.35±0.04×10−4Ωcm. Based on the results, a 3D multi-layered circuit system was manufactured with the HDPE as the substrate/matrix material and copper/HDPE mixture as the conductive-track material. This circuit system was successfully manufactured, demonstrating the possibility of using SLM technology to manufacture dissimilar materials towards 3D electronic applications.

Packaging of High-Gain Multichip Module in Multilayer LCP Substrates at $W$ -Band

In this paper, we packaged a multichip module (MCM) in multilayer liquid crystal polymer (LCP) substrate using V-shaped wire bond and 3-D-printed housing. In the proposed module, two low-noise amplifiers (LNAs) are cascaded in series to obtain high gain and low noise figure, and multilayer circuit is designed to achieve high assembly density. To minimize mode mismatch between microstrip lines on LNA and LCP with low dielectric constant, V-shaped wire bond was designed for LNA integration, achieving low insertion loss and low reflection at $W$ -band. To verify this bonding design experimentally, a single-chip module was first integrated and characterized, successfully achieving a gain of more than 26.5 dB from 80 to 100 GHz. Then, the MCM was investigated and packaged, in which substrate integrated waveguides and via barriers are introduced to eliminate the potential substrate modes, and 3-D-printed plastic housing coated with gold is designed to capsulate the LNAs and isolate them in free space. The measured data demonstrate a high gain of 50 dB, a low noise figure of less than 6 dB, and linear phase from 80 to 97 GHz.

Frequency independent 180° phase shifter based on UWB coupled sections

AbstractIn this article, a novel Ultra‐Wideband (UWB) 180° planar phase shifter is designed and fabricated. The proposed design is mainly based on coupled sections which are realized by inserting slots into the common ground plane of the multilayer circuit. Two identical structures, leading to discard parameters that disturb the output phase shift, are introduced in the design. To get 180° phase difference shift, via holes are used to perform a short circuit in one of the two coupled sections. Theoretical analysis based on four port network is presented to explain the characteristics of the proposed design. Further, experimental measurements are performed and compared with simulation results to validate the proposed approach. Hence, a good simulated to measured agreement is obtained.

Analysis, Design and Optimization of Multilayer Antenna Using Wave Concept Iterative Process

The wave concept iterative process is a procedure used for analyses a planar circuits This method consists in generating a recursive relationship between a wave source and reflected waves from the discontinuity plane which is divided into cells. A high computational speed has been achieved by using Fast Modal Transform (FMT). In this paper we study a patch antenna and multilayer circuits, to determine the electromagnetic characteristics of these structures.