Multi-input Gates Research Articles

Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low-power option for CMOS systems-on-a-chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow-transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive-feedback adiabatic logic (PFAL), two-level adiabatic logic (2-LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2-LAL are presented. The problem with 2-LAL multi-input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context—a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions.

The Involution Tool for Accurate Digital Timing and Power Analysis

We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping.We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates.

Multi-input volistor logic XNOR gates

ABSTRACT A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology – the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power. Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S 1 and S 2 through horizontal wires W in1 and W in2, and the output which is logical AND of states S 1 and S 2 is calculated by applying V READ to vertical wire W XNOR. (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches.

A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function

Great attention is paid to develop the nanotechnology fabrication techniques, but few attempts were done to develop special design techniques for the emerging nanotechnologies. In this paper, a new design approach for the multi-input XOR suitable for nanotechnologies is presented. This approach uses the multi-input majority function as a building block. The proposed method causes significant improvement in the gate level. The proposed design approach is deployed to CNFET 5-input and 7-input XOR circuit. The results show good improvements in the speed and number of devices.

MODELING THE OVERSHOOTING EFFECT OF MULTI-INPUT GATE IN NANOMETER TECHNOLOGIES

With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

Scalable minority gate: a new device in two-dot molecular quantum-dot cellular automata

Design for scalability is one of the paramount aspects of nanotechnology. The authors present a new architecture for scalable gates in two-dot molecular quantum-dot cellular automata paradigm. Quantum chemical calculations are performed on multiple molecules that are arranged to carry out logic operations at the nanoscale. Compared to previous multi-input gates in four-dot quantum-dot cellular automata framework, the number of used redox centres has been significantly reduced in the presented gates.

Position-sensing detector for logical operations using incoherent light

The application of a position-sensing detector to optical logic operations has been introduced and experimentally demonstrated for the first time. We describe some possible architectures for all 16 two-input Boolean gates as well as for multi-input gates.

Development of silicon single-electron devices

We have developed a novel method called pattern-dependent oxidation (PADOX) for fabricating small Si single-electron transistors (SETs) and used it to make many kinds of SEDs. One of the most primitive and important features of the method is that fabricated devices operate quite stably for long-term drift. By using the method we have demonstrated various kinds of logic devices. SETs have two unique features that conventional transistors do not have. One is multi-input gates capability, and the other is oscillatory conductance as a function of gate voltage. We have exploited these features to achieve complicated functions, such as an adder and a multiple-valued memory.

A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (g/sub m/) of 470 /spl mu/S//spl mu/m at V/sub D/=1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in an application to multi-input NAND gates was investigated.

Multi-Input Floating Gate Differential Amplifier and Application to Intelligent Sensors

Multi-input floating gate differential amplifier (FGDA) is proposed which can perform any convolution operation with differential structure and feedback loop. All operations are in the voltage mode. Only one terminal is required for the negative feedback which can suppress distortions due to mismatches of active elements. Possible applications include intelligent image sensor, where fully parallel DCT operation can be performed. A prototype chip is fabricated which is functional. A preliminary test result is reported.

CMOS multi-input gate implementations for low-power digital design

Power consumption is one of the most critical design parameters in analogue and digital circuits. This paper studies different static CMOS implementations of digital logic functions with power and power-delay product as criteria. Two approaches are used. The first one compares the implementation styles by introducing new probabilistic methods in estimating the average power dissipation (dynamic and short-circuit). The second one uses statistics, based on power and delay measurements, to achieve more accurate results. Both approaches indicate the same conclusions in an example of two different implementations of a six-input NAND gate.

Multi-input Josephson AND gate with ladder structure

A multi-input AND gate composed of multiple stages, each with a three-junction interferometer and a single junction (ladder structure) is proposed. The number of inputs to this multi-input with multi-stage AND gate can easily be extended by systematically increasing the number of stages without decreasing the operating margin. The design and experimental results are described. Operating margins of the six-input AND gate were +or-30% (from simulation) and +or-20% (from experiment). The operating speed, simulated for 2.5- mu m-diameter junctions, was 60 ps, whereas the measured speed was 130 ps. The difference seems to be due to circuit parameter spread because the chip used for measuring the speed had large critical current deviation. >

An Efficient Timing Model for CMOS Combinational Logic Gates

A new general timing model for CMOS combinational logic gates is proposed. In this model, the linearized large-signal equivalent circuit of a gate is first constructed. Then applying the dominant-pole-dominant-zero (DPDZ) method, the dominant pole of the equivalent circuit is calculated. Using this pole, the signal timing can be explicitly expressed. Comparisons between calculation results and simulation results are made and error analyses are performed. The worst-case error in characteristic-waveform timing can be confined to be within 35 percent for CMOS inverters, multi-input NOR gates or multi-input NAND gates with different device dimensions, capacitive loads, and device parameters. Better accuracy can be obtained for logic gates with commonly-used channel dimension or large capacitive load. For internal waveforms not deviating much from the characteristic waveforms, the worst-case error in signal timing is not substantially increased. Applying the proposed timing model in an experimental timing simulator, the signal timing can be analyzed accurately and efficiently with reduced CPU time and memory.

MACTIS-A mask checking timing simulator

A new timing simulator is described for mask design verification of MOS/LSI before fabrication. Each circuit node is treated as the output of a multi-input transmission gate. Applying a macromodel technique to this transmission gate, it is possible to perform cost-effective timing simulation of the LS1 having up to 10 000 transistors.

MACLOS-mask checking logic simulator [for MOS LSI

A new logic simulator is described which uses the output from a mask analysis program as the input circuit data. Each circuit node is treated as the output of a multiinput transfer gate. Three logical states: 0, 1, and X, and four auxiliary states: D, S, B, and Z, are used in the simulation with a unit gate delay. The circuit node in the E/D MOS LSI is sorted into two types. The one, named TG, looks like the output of a multiinput transfer gate, and the other, named PTG, is like a transfer gate with a pulling-up transistor. MACLOS was successfully applied to a 12-bit microprocessor chip including 10K transistors and a RAM block fabricated by the E/D MOS process. It took 25 min for ACOS 700 to simulate the microprocessor for 213 clock cycles; 49K words of core memory were used in the simulation.