Double-gate Research Articles

Impacts of Cavity Thickness and Insulating Material on Dielectric Modulated Trench Junction-less Double Gate Field Effect Transistor for Biosensing Applications

Introduction: This work represents the influence of gate dielectric, and the nano-cavity gap of a dielectric modulated trench gate Junction-less Double Gate Field Effect Transistor (JL-DGFET) on the different performance indicators is investigated considering the Low-Frequency Noise. Methods: It is noted that the gate dielectric and the nanogap, both parameters, have a substantial influence on the sensing capacity and performance of noise of the device. Results: A double gate suitable dielectric material and cavity thickness can effectively improve the biosensor’s sensitivity with a minimum amount of noise. Conclusion: The sensitivity is found to increase up to 9.5 for dielectric constant, k = 3.57 and 6.5 for dielectric constant, k = 2.1.

An analytical I-V model of SiC double-gate junctionless MOSFETs

Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.

Impact of high-k insulators on electrical properties of junctionless double gate strained transistor

High-k dielectric insulators are required to reduce leakage and increase transistor performance. They are able to impact the mobility of carriers in transistors positively, leading to better device performance in advanced transistor architecture. Nevertheless, an in-depth analysis of how high-k dielectric insulators influence transistor characteristics must be carried out to determine their suitability. The objective of this study is to investigate the impact of high-k insulators towards electrical properties of junctionless double gate strained transistor. The simulation works is done using process/device simulator Silvaco Athena/Atlas. Based on the retrieved results, the magnitude of I<sub>ON</sub>, on-off ratio, g<sub>m</sub>, and C<sub>int</sub> for TiO<sub>2</sub>-based device are approximately 63%, 99%, 62%, and 89% respectively higher than the lowest permittivity material-based device. The TiO<sub>2</sub>-based device also exhibits the lowest magnitude in I<sub>OFF</sub> and SS compared to others. However, a significant degradation in f<sub>T</sub> magnitude have been observed for TiO<sub>2</sub>-based device significantly due to its large capacitances

Development and investigation of DMDG-MOSFET biosensor for charged biomolecule detection

Abstract The paper explores the analog and sensitivity parameter of a n-channel gate stack Dual Material Double Gate (DMDG) MOSFET biosensor, specifically focusing on its response to a wide range of charged biomolecule introduced into its cavity region. This novel structure offers improved sensitivity and selectivity due to its ability to modulate the threshold voltage and control the electrostatic environment more precisely compared to conventional MOSFET-based biosensors. The analysis includes a thorough examination of the surface potential, electric field, transconductance, and threshold voltage variations influenced by the presence of charged biomolecules. By applying a parabolic-potential technique to solve the 2-D Poisson's equation, the expression for surface potential can be found. The minimal surface potential model is used to calculate the threshold voltage. Using SILVACO ATLAS, the simulation findings suggest that the proposed gate stack DMDG-MOSFET structure demonstrates sensitivity of 0.123 V and 0.607 V for neutral and charged biomolecules respectively emphasizing the impact of gate material engineering on the biosensor's performance.

The FinFET effect in lateral 4H-SiC and Silicon multi-gate MOSFETs

Abstract This paper presents a comprehensive investigation on the role and manifestation of the FinFET effect in low voltage 4H-SiC MOSFETs as compared to their Si counterparts. For this purpose, a finite element model of a fabricated SiC FinFET with a fin width of 55 nm is constructed and calibrated to experimental data at a range of operating temperatures. The resulting TCAD model is then applied to examine the impact of the FinFET effect on the threshold voltage and the spatial variation of the carrier density and the drift mobility in the channel for a range of doping concentrations N A of the p-well. It is thereby shown that by reducing the fin width W fin from conventional values ≳ 500 nm down to an interval of optimal values ∼40 nm (keeping everything else constant), it is possible to enhance the channel mobility ∼2.5 times. This improvement is not only found to be much larger than the one predicted in Si (where it is ∼ 15% according to the TCAD model) but also arises at a larger fin width (for a given N A ). In this respect, it is demonstrated that this optimal range of fin widths can be moved to even larger, more practical values by reducing the doping of the p-well. As an alternative, the on-state performance of the gate-all-around FET is also examined in detail following a similar procedure. It is hence shown that this structure can display the FinFET effect at an even larger, nearly conventional W fin of ∼250 nm, whilst attaining a higher channel mobility and inversion layer density even than a stripe FinFET operated at the same overdrive. Thus, in light of all these advantages, the FinFET topology can play a key role in reducing the channel resistance of SiC power MOSFETs.

Device Reliability of Negative Capacitance Source Pocket Double Gate TFETs: A Study on Temperature and Noise Effects

Abstract This study investigates the reliability of a negative capacitance source pocket double gate tunnel field-effect transistor (NC-SP-DGTFET) by examining the effects of temperature and various noise components on its performance. The research focuses on key DC parameters, including the transfer characteristics, subthreshold swing, and the ION/IOFF ratio, evaluated across a temperature range from 250 to 450 K. Additionally, the study explores the radio-frequency performance of the device by assessing how temperature impacts transconductance (gm), cut-off frequency (fT), gate capacitance (Cgg), intrinsic delay, and the transconductance frequency product. Noise performance metrics are also analyzed, focusing on the drain current noise power spectral density (SID) and gate voltage noise power spectral density (SVG). The study considers the contributions of diffusion, generation-recombination (G-R), and flicker noise components and at 300 K, SID and SVG showed peak values of 5.08×10-26 A²/Hz and 2.67×10-16 V²/Hz, 5.73×10-18 A²/Hz and 3.22×10-10 V²/Hz, and 1.33×10-25 A²/Hz and 1.19×10-14 V²/Hz, respectively. The analysis reveals that flicker noise is predominant at lower frequencies, while diffusion noise becomes more significant at higher frequencies. However, G-R noise is the most dominant across all frequencies examined. These findings provide crucial insights for optimizing the design and performance of NC-SP-DGTFETs in low-power applications.

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Optimized Gate Metal Variant Structure for Graded-Channel (GC) Gate-Stack (GS) Double-Gate (DG) MOSFET to Enhance Switching Speed, Analog and RF Performance

Analysis on density of states and ION/IOFF ratio of GaN/GaN-graphene nanoribbon tunnel FET for enhanced bio-sensing applications

Abstract This research introduces a new analytical model that studies the effect of ferro-dielectric on the operational performance of TFETs doped with halogens. The effect of source and drain depletions, voltage-drain & gate, thickness and capacitance of gate insulator are all investigated in this study. Accurate measurements of the surface potential are required to ascertain the transconductance, gate-to-drain capacitance, and lateral electric field of the device. Our model, which employs Ferroelectric Halo-Doped double gate (FHDD)-gated device designs, has been demonstrated to produce results that nearly match those produced from TCAD simulations. This was accomplished by doing a comparative analysis of the outcomes derived from both sets of simulations. Furthermore, the performance of the suggested structure of TFET, which integrates a dielectric of Fe and GaN heterostructure, surpasses that of other similar devices (fT) in terms of ON current, ON/OFF ratio, transconductance, and cut-off frequency. A ferroelectric dielectric was used to create a ferroelectric heterostructure. This study also centers on the creation and application of a graphene nanoribbon field effect transistor (GNR-TFET) to detect sugar molecules, specifically fructose, xylose, and glucose. The detecting signal is generated by utilizing the fluctuation in the electrical current of the GNR-TFET caused by the presence of individual sugar molecules. The GNR-TFET exhibits noticeable variations in the density of states, transmission spectrum, and current when exposed to individual sugar molecules. The sensor under investigation is being developed and examined using a combination of semi-empirical modeling and non-equilibrium Green's functional theory (SE + NEGF). According to the research, the modified GNR TFET has the ability to quickly and accurately detect individual sugar molecules in real-time.

Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

Abstract Ternary adders have produced more benefits compared to binary adders i.e., the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32 nm. At 32 nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. Carbon Nano-tube Field Effect Transistors (CNFETs) are one of the technologies to work efficiently when the channel length is 32 nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances energy efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as Gate Diffusion Input (GDI) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the Power Delay product (PDP) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.

Enhanced Performance of Dual Material Double Gate Negative Capacitance Tunnel Field Effect Transistor (DMDG‐NC‐TFET) via HZO Ferroelectric Integration for Improved Drain Current and Subthreshold Swing

ABSTRACTThis paper developed the novel structure of a dual material double gate negative capacitance tunnel field effect transistor (DMDG‐NC‐TFET) using HZO ferroelectric material. This study systematically improved the drain current and subthreshold swing (SS) by inducing a negative capacitance effect in a gate stack. The proposed gate oxide structure is a stack configuration of ferroelectric material, and high‐k dielectric to improve gate control. The Landau–Khalatnikov (LK) equation is used to solve the Poisson equation and get an accurate estimate of the channel potential. Kane's model is used for band‐to‐band generation rate calculation. For modelling the drain current, the band‐to‐band tunnelling (Gbtbt) generation rate is integrated using the entire device volume. The impact of varying ferroelectric thickness in the proposed structure has been investigated with the simulated results. The outcomes demonstrate that the device can obtain better improvements in ON current and SS, compared to conventional DMDG‐TFET. By contrasting the analytical results with the outcomes of the TCAD simulation, the effectiveness of the proposed methodology has been demonstrated.

Tunable two-photon THz emissions through pair annihilation in graphene with a double gate structure

How far the analogy between massless Dirac fermions in a truly relativistic (1+2)-D spacetime and electrons near the Fermi level in graphene can be seriously taken? A hallmark of relativistic QFT is the multi-photon emission through pair annihilation. In this paper, to address this question we formulate the theoretical basis for a double gate graphene device. In an infinite sheet of pristine graphene the Fermi level is located at the Dirac points, but it can be tunned through gate potentials. This way, electron and hole pockets are induced, forming N and P regions in a large monolayer graphene sheet. The quasi-particles can be accelerated through the source-drain potential to scatter at an intrinsic region, leading to electron-hole annihilation. Feynman amplitudes and emission rates for two-photon emissions arising from electron-hole annihilation in graphene are presented at lowest order, leading to analytical formulae for two photon production, which could experimentally be tested.

Study of A Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel FET combining analytical modeling and TCAD simulation

A short channel Heterojunction Double Gate Ferroelectric p-n-i-n Tunnel Field Effect Transistor structure is proposed in this article to alleviate undesirable ambipolarity and Miller Capacitance and has a steeper subthreshold swing with improvement in ON state current compared to other conventional TFET structures. This work develops a physics based relevant analytical model of surface potential with the effect of gate fringing field and inclusive source and channel depletion region, drain current model, terminal charge and capacitance model to investigate its transient performance for the impact of ferroelectric polarization according to the Miller Ferroelectric polarization model. The proposed device is also validated using the SILVACO ATLAS device simulator, which yields a good agreement with the model, establishing its reliability and acceptability. The device achieves a steeper subthreshold of 31.3 mV/decade, an improved ON current∼5.9 x 10−4A/μmand enhanced transconductance∼0.105 ms as well as a very low energy delay product (EDP)∼4.07 x 10−3Js with hysteresis free operation at a low supply voltage∼0.5 V in a 40 nm technology node, making it desirable for ultra-low power analog and logic applications.

Flexible p-Type WSe2 Transistors with Alumina Top-Gate Dielectric.

Tungsten diselenide (WSe2) field-effect transistors (FETs) are promising for emerging electronics because of their tunable polarity, enabling complementary transistor technology, and their suitability for flexible electronics through material transfer. In this work, we demonstrate flexible p-type WSe2 FETs with absolute drain currents |ID| up to 7 μA/μm. We achieve this by fabricating flexible top-gated FETs with a combined WSe2 and metal contact transfer approach using WSe2 grown by metal-organic chemical vapor deposition on sapphire. Despite moderate WSe2 crystal grain size, our devices show similar or higher |ID| and ID on/off ratio (∼105) compared to most devices with exfoliated single-crystal WSe2 from the literature. We analyze charge trapping in our devices using pulsed and bias stress measurements. Notably, the high |ID| values are preserved during pulsing, where charge trapping is minimized. Overall, we demonstrate a fabrication approach advantageous for high drain currents in flexible 2D transistors.

2D transistors feel the strain

2D transistors feel the strain

Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

Performance Analysis of JL-FinFET with Varied Non-Uniform Doping Concentrations, Fin Height and Fin Width using Device Simulator

With the growth of the MOSFET technology, the size of the transistor becomes smaller which can lead to Short-Channel Effects (SCEs). In order to address the SCEs, multi-gate transistor such as Fin Field-Effect Transistor (FinFET) has been invented. Meanwhile, it is found that the conventional transistor with junctions also has its drawbacks and limitations due to the decrease in the gate length. The SCEs can occur and affect the overall performance of the device with lower switching times and lower current density . In order to address these limitations, new structure of transistor without junction known as a junctionless (JL) transistor has been proposed. In this work, the impact of uniform versus non-uniform doping concentrations, fin height (Hfin) and fin width (Wfin) in JL-FinFET were investigated by using Technology Computer Aided Design (TCAD) Tools. It was found that non-uniform doping concentration of 4 x1018 cm-3 for the source/drain and of 4 x1017 cm-3 for the channel, together with Hfin of 20 nm and Wfin of 4 nm provide the best electrical performance of Ioff = 6.45 x10-17 A, Ion = 6.14 x10-6 A, Ion/Ioff = 9.52 x1010 and DIBL = 11 mV/V. The outcome of this research work can be used as a basis to understand JL-FinFET biosensors for medical applications and more complex JL structures.

Virtual Fabrication of 14nm Gate Length n-Type Double Gate MOSFET

Due to Moore's law, it is that predicted the channel length of a metal-oxide-semiconductor Field Effect Transistor (MOSFET) will tend to shrink from the submicron to the nanoscale size. Thus, precision in the manufacturing process has become crucial. This study describes the virtual fabrication as well as the electrical characteristics of a 14nm NMOS double gate with a bilayer graphene/high-K/metal gate. In this device, Hafnium Dioxide (HfO2) is employed as a high-k material, and Tungsten Silicide (WSix) is used as a metal gate. Several Silvaco TCAD Tools, including ATHENA and ATLAS, were utilized in the fabrication and simulation of the device, respectively. According to the simulation results, the optimal threshold voltage (VTH), drive current (ION), and leakage current (IOFF) and subthreshold slope (SS) values are 0.2059 V, 797.5650 μA/μm. 29.5794 nA/μm, and 89.1712x10-3 V respectively. The findings of this research showed that the efficiency of this 14nm double gate n-type MOSFET device is satisfactory because the threshold voltage and leakage current parameters are in accordance with ITRS 2013, and that it may have been utilized as a utility man in future modelling and optimization efforts.

Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling

We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (Vth) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of Vth, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.

Enhanced Biosensing with Double Gate Junctionless FET based on III–V Compound Semiconductor and Symmetric Cavity for Label-Free Detection of Neutral and Charged Biomolecules

Enhanced Biosensing with Double Gate Junctionless FET based on III–V Compound Semiconductor and Symmetric Cavity for Label-Free Detection of Neutral and Charged Biomolecules

All-Ferroelectric Spiking Neural Networks via Morphotropic Phase Boundary Neurons.

Artificial neurons and synapses are crucial for efficiently implementing spiking neural networks (SNNs) in hardware. The distinct functional requirements of artificial neurons and synapses present significant challenges in the implementation of area- and energy-efficient SNNs. This study reports an all-ferroelectric SNN system through co-optimization of material properties and device configurations using wafer-scale atomic layer deposition. For the first time, a double-gate (DG) morphotropic phase boundary-based thin-film transistor (MPBTFT) is utilized for a leaky integrate-and-fire (LIF) neuron. The DG MPBTFT-based LIF neuron eliminates the need for capacitors and reset circuits, thereby enhancing area and energy efficiency. The DG configuration demonstrates various neuronal functions with high reliability. Co-optimizing materials and devices significantly enhance the performance and functional versatility of artificial neurons and synapses. Meticulous material engineering facilitates the seamless co-integration of DG MPBTFT-based neurons, ferroelectric thin-film transistor (TFT)-based synapses, and normal TFTs on a single wafer. All-ferroelectric SNN systems achieved a high classification accuracy of 94.9%, thereby highlighting the potential of DG MPBTFT-based LIF neurons for advanced neuromorphic computing.