Multiprocessor Systems Research Articles

An Innovative Topologies Based on Hypercube Network Interconnection

A parallel processing system's most crucial part is a network interconnection that links its processors. The hypercube topology has interesting features that make it a great option for parallel processing applications. This paper presents two innovative configurations of interconnection networks based on fractal Sierpinski and a hypercube. These are called the Sierpinski Triangle Topology (STT) and Sierpinski Carpet Topology (SCT). Compared to a hypercube, the Sierpinski Triangle topology (STT) noticed a significant decrease in the number of nodes and links as large networks grew. Hence, it is considered a great way to reduce costs because it uses fewer nodes and links. The average distance is also shorter, which is better. Despite it having a smaller bisection width and a higher degree than a hypercube by one. The Sierpinski Carpet Topology (SCT) has the advantage of having a high bisection width compared to a hypercube. That is preferable because it places a lower restriction on the difficulty of parallel algorithms. While the drawback of this topology is that it has a diameter and average distance more than a hypercube.

Retracted: Low-Power Task Scheduling Algorithm for the Multicore Processor System Based on the Genetic Algorithm

Retracted: Low-Power Task Scheduling Algorithm for the Multicore Processor System Based on the Genetic Algorithm

MaGNAS: A Mapping-Aware Graph Neural Architecture Search Framework for Heterogeneous MPSoC Deployment

Graph Neural Networks (GNNs) are becoming increasingly popular for vision-based applications due to their intrinsic capacity in modeling structural and contextual relations between various parts of an image frame. On another front, the rising popularity of deep vision-based applications at the edge has been facilitated by the recent advancements in heterogeneous multi-processor Systems on Chips (MPSoCs) that enable inference under real-time, stringent execution requirements. By extension, GNNs employed for vision-based applications must adhere to the same execution requirements. Yet contrary to typical deep neural networks, the irregular flow of graph learning operations poses a challenge to running GNNs on such heterogeneous MPSoC platforms. In this paper, we propose a novel unified design-mapping approach for efficient processing of vision GNN workloads on heterogeneous MPSoC platforms. Particularly, we develop MaGNAS, a mapping-aware Graph Neural Architecture Search framework. MaGNAS proposes a GNN architectural design space coupled with prospective mapping options on a heterogeneous SoC to identify model architectures that maximize on-device resource efficiency. To achieve this, MaGNAS employs a two-tier evolutionary search to identify optimal GNNs and mapping pairings that yield the best performance trade-offs. Through designing a supernet derived from the recent Vision GNN (ViG) architecture, we conducted experiments on four (04) state-of-the-art vision datasets using both ( i ) a real hardware SoC platform (NVIDIA Xavier AGX) and ( ii ) a performance/cost model simulator for DNN accelerators. Our experimental results demonstrate that MaGNAS is able to provide 1.57 × latency speedup and is 3.38 × more energy-efficient for several vision datasets executed on the Xavier MPSoC vs. the GPU-only deployment while sustaining an average 0.11% accuracy reduction from the baseline.

A Comparative Study on the Schedulability of the EDZL Scheduling Algorithm on Multiprocessors

As multiprocessor (or multicore) real-time systems become popular, there has been much research on multiprocessor real-time scheduling algorithms. This work evaluates EDZL (Earliest Deadline until Zero Laxity), a scheduling algorithm for real-time multiprocessor systems. First, we compare the performance of EDZL schedulability tests. We measure and compare the ratio of task sets admitted by each test. We also investigate the dominance between EDZL schedulability tests and discover that the union of the demand-based test and the utilization-based test is an effective combination. Second, we compare the schedulability of EDZL and EDF(k). We prove that the union of the EDZL schedulability tests dominates the EDF(k) schedulability test, i.e., the union of the EDZL schedulability tests can admit all task sets admitted by the EDF(k) schedulability test. We also compare the schedulability of EDZL and EDF(k) through scheduling simulation by measuring the ratio of successfully scheduled task sets. EDZL can successfully schedule 7.0% more task sets than EDF(k).

Report on the exact methods for finding minimum-sized DFA

Abstract This paper presents four state-of-art methods for the finite-state automaton inference based on a sample of labeled strings. The first algorithm is Exbar, and the next three are mathematical models based on ASP, SAT and SMT theories. The potentiality of using multiprocessor computers in the context of automata inference was our research’s primary goal. In a series of experiments, we showed that our parallelization of the exbar algorithm is the best choice when a multiprocessor system is available. Furthermore, we obtained a superlinear speedup for some of the prepared datasets, achieving almost a 5-fold speedup on the median, using 12 and 24 processes.

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved. We provide a new arbitration method that prioritizes the pending refresh requests according to their level of urgency and optimizes the allocation of GC-eDRAM resources in order to guarantee that refresh operations are carried out in an effective manner. Our method modifies the arbitration priority in a dynamic manner according to the characteristics of the active workload. These characteristics include the request arrival rate, memory access patterns, and data location, among other considerations.

The TETRISC SoC—A resilient quad-core system based on the ResiliCell approach

Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. This paper presents an approach for enabling a design to achieve resilience. By using a range of reliability sensors and the novel ResiliCells, we have developed the TETRISC System-on-Chip (SoC), which is a multiprocessor system based on the PULPissimo platform. The TETRISC SoC can operate its four cores in different performance and fault tolerance modes based on real-time data, making it ideal for use cases with dynamically changing and reliability critical requirements, such as avionics or aerospace. Additional in-depth studies on possible optimizations demonstrate the flexibility of the ResiliCell approach.

Reliability analysis of 3-ary [formula omitted]-cube in terms of average degree edge-connectivity

Classical edge-connectivity is a vital metric to characterize fault tolerance and reliability of network-based multiprocessor system. As two generalizations of classical edge-connectivity, super edge-connectivity and average degree edge-connectivity are two important parameters to assess the fault tolerability of a multiprocessor system by imposing some constraints on the degree of survival graph. In this work, we focus on k-super edge connectivity λk(Qn3) and a-average degree edge connectivity λa¯(Qn3) of the 3-ary n-cube. We first show that λ2a¯(Qn3)=2(n−a)3a for 0≤a≤n−1, n≥1 and λ2a+1¯(Qn3)=2(2n−2a−1)3a for 0≤a≤n−2, n≥2. Moreover, we determine that λ2a(Qn3)=λ2a¯(Qn3), and λ2a+1(Qn3)=λ2a+1¯(Qn3), which indicates that these two kinds of metrics possess the same robustness in a 3-ary n-cube.

Fully automated annotation of mitochondrial genomes using a cluster-based approach with de Bruijn graphs.

A wide range of scientific fields, such as forensics, anthropology, medicine, and molecular evolution, benefits from the analysis of mitogenomic data. With the development of new sequencing technologies, the amount of mitochondrial sequence data to be analyzed has increased exponentially over the last few years. The accurate annotation of mitochondrial DNA is a prerequisite for any mitogenomic comparative analysis. To sustain with the growth of the available mitochondrial sequence data, highly efficient automatic computational methods are, hence, needed. Automatic annotation methods are typically based on databases that contain information about already annotated (and often pre-curated) mitogenomes of different species. However, the existing approaches have several shortcomings: 1) they do not scale well with the size of the database; 2) they do not allow for a fast (and easy) update of the database; and 3) they can only be applied to a relatively small taxonomic subset of all species. Here, we present a novel approach that does not have any of these aforementioned shortcomings, (1), (2), and (3). The reference database of mitogenomes is represented as a richly annotated de Bruijn graph. To generate gene predictions for a new user-supplied mitogenome, the method utilizes a clustering routine that uses the mapping information of the provided sequence to this graph. The method is implemented in a software package called DeGeCI (De Bruijn graph Gene Cluster Identification). For a large set of mitogenomes, for which expert-curated annotations are available, DeGeCI generates gene predictions of high conformity. In a comparative evaluation with MITOS2, a state-of-the-art annotation tool for mitochondrial genomes, DeGeCI shows better database scalability while still matching MITOS2 in terms of result quality and providing a fully automated means to update the underlying database. Moreover, unlike MITOS2, DeGeCI can be run in parallel on several processors to make use of modern multi-processor systems.

Machine learning in run-time control of multicore processor systems

Abstract Modern embedded and cyber-physical applications consist of critical and non-critical tasks co-located on multiprocessor systems on chip (MPSoCs). Co-location of tasks results in contention for shared resources, resulting in interference on interconnect, processing units, storage, etc. Hence, machine learning-based resource managers must operate even non-critical tasks within certain constraints to ensure proper execution of critical tasks. In this paper we demonstrate and evaluate countermeasures based on backup policies to enhance rule-based reinforcement learning to enforce constraints. Detailed experiments reveal the CPUs’ performance degradation caused by different designs, as well as their effectiveness in preventing constraint violations. Further, we exploit the interpretability of our approach to further improve the resource manager’s operation by adding designers’ experience into the rule set.

Prioritized Time-Point-Interval Petri Nets Modeling Multiprocessor Real-Time Systems and TCTL$_{x}$

When a group of real-time tasks with dependent relations are performed in parallel in a multi-processor interruptible environment, time-related requirements are easily destroyed so that the correct design of such a system is complex and difficult. Therefore, it is necessary for designers to use some precise methods to verify their correctness, while model checking based on time Petri nets and timed computation tree logic (TCTL) is such an effective method. However, the existing models and tools only focus on those multi-processor real-time systems where the number of processors of the same type is just one, and thus they cannot work for the case that the number of processors of the same type is greater than one. Hence, this paper proposes prioritized time-point-interval Petri nets (PToPN) to deal with it and defines their firing rules and state graphs to represent their behaviors. A PToPN can explicitly model the preemptive scheduling of such a real-time system, and TCTL formulas specifying design requirements of the system can be verified based on its state graph. Besides, we propose TCTL with unknown time bounds, denoted as TCTL <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{x}$</tex-math></inline-formula> , to compute the minimum or maximum time bound ensuring a related formula holds. Such a quantitative analysis is very necessary in the real applications because they can be used to compute some performances of a system such as the worst-case execution time of tasks and the idle time of processors. We design the related algorithms and develop a tool. We use a real example from HUAWEI Company to show the usefulness of our method, and do some experiments to show the advantages of our method compared with another state-of-the-art one.

Application Level Resource Scheduling for Deep Learning Acceleration on MPSoC

Deep Neutral Networks (DNNs) have been widely used in many applications, such as self-driving cars, natural language processing (NLP), image classification, visual object recognition, and so on. Field-programmable gate array (FPGA) based Multiprocessor System on a Chip (MPSoC) is recently considered one of the popular choices for deploying DNN models. However, the limited resource capacity of MPSoC imposes a challenge for such practical implementation. Recent studies revealed the trade-off between the “resources consumed" vs. the “performance achieved". Taking a cue from these findings, we address the problem of efficient implementation of deep learning into the resource-constrained MPSoC in this paper, where each deep learning network is run with different service levels based on resource usage (where a higher service level implies higher performance with increased resource consumption). To this end, we propose a heuristic-based strategy, Application Wise Level Selector (AWLS), for selecting service levels to maximize the overall performance subject to a given resource bound. AWLS can achieve higher performance within a constrained resource budget under various simulation scenarios. Further, we verify the proposed strategy using an AMD-Xilinx Zynq UltraScale+ XCZU9EG SoC. Using a framework designed to deploy multi-DNN on multi-DPUs (Deep Learning Units), it is proved that an optimal solution is achieved from the algorithm, which obtains the highest performance (Frames Per Second) using the same resource budget.

Hyper [formula omitted] and sub-[formula omitted] fault tolerance of star graphs

Given a connected subgraph H of an interconnection network G, the H-structure connectivity κ(G;H) and the H-substructure connectivity κs(G;H) of G are two important measurements for fault tolerance of G. The n-dimensional star graph Sn is an attractive interconnection network candidate for multiprocessor systems, and it is (n−1)-regular. Let n≥4 and 0≤r≤n−1. In this paper, we prove that (i)κ(Sn;K1,r)=κs(Sn;K1,r)=n−1, and (ii) the removal of any minimum K1,r-cut (or, minimum sub-K1,r-cut) will split Sn into exactly two components, one of which is a singleton, where K1,r is a tree on 1+r vertices, r of which are leaves. The main results generalize some known ones.

Probabilistic Fault Diagnosis of Clustered Faults for Multiprocessor Systems

Probabilistic Fault Diagnosis of Clustered Faults for Multiprocessor Systems

Parallelization of numerical solutions of shallow water equations by the finite volume method for implementation on multiprocessor systems and graphics processors

An overview of approaches to parallelization of grid-based numerical methods for solving shallow water equations for multiprocessor systems and graphics processors is presented. A multithreaded approach for shared-memory computing systems implemented on the basis of the OpenMP programming interface and a geometric decomposition approach with message-passing using the MPI library for distributed-memory computers are described. Multithreading for programming GPUs based on the OpenACC software interface is considered. For the COASTOX-UN system of two-dimensional modeling of hydrodynamics, sediment and radionuclide transport in river systems and coastal areas of the seas, the parallelization of its hydrodynamic model COASTOX-HD was carried out. In the developed numerical model, the shallow water equations are solved by finite-volume numerical methods on unstructured computational grids with triangular cells of variable size. The parallelization is implemented using a hybrid MPI+OpenACC approach targeting multiprocessor systems and GPUs. For multiprocessor computers, geometric decomposition and MPI-based messaging are used, and for GPUs, multithreading is implemented using OpenACC directives. The performance of the developed parallel hydrodynamic model was evaluated during the calculation of typical problems of hydrodynamics of shallow water bodies, river flood, and tsunami wave run-up on the coast on a Dell Precision Workstation 7920 multi-core workstation with two 20-core Intel Xeon Gold 6230 processors and NVIDIA Quadro RTX 5000 and NVIDIA GeForce RTX 3080 graphics cards. It is shown that the developed model has significantly accelerated the simulation on the considered multiprocessor system and the considered GPUs. The acceleration on GPUs depends on the size of the computational grid, increasing to saturation with an increase in the number of grid cells. It is established that for the developed parallel model, whose numerical schemes are related to algorithms with low computational intensity, the memory bandwidth of the NVIDIA architecture GPUs is a more important limiting factor of acceleration than their performance.

Recursive definition and two edge-disjoint Hamiltonian cycles of bubble-sort star graphs

The bubble-sort star graph is an interconnection network for multiprocessor systems. Recursive structure is important for interconnection networks, since it can reduce the complex cases into simple cases, and it can keep good properties independent of dimensions. Many algorithms use the idea of recursive construction. Edge-disjoint Hamiltonian cycles not only provide the basis of all-to-all broadcasting algorithm for networks but also provide a replaceable Hamiltonian cycle for transmission when the other Hamiltonian cycle contains faulty edges in an interconnection network. In this paper, we propose the recursive definition of bubble-sort star graphs. Then as an application, we obtain two edge-disjoint Hamiltonian cycles of bubble-sort star graphs.

GEOSPATIAL BIG DATA ANALYTICS FOR SUSTAINABLE SMART CITIES

Abstract. Growing urbanization cause environmental problems such as vast amount of carbon emissions and pollution all over the world.Smart Infrastructure and Smart Environment are two significant components of the smart city paradigm that can create opportunities for ensuring energy conservation, preventing ecological degradation, and using renewable energy sources. Since a great portion of the data contains location information, geospatial intelligence is a key technology for sustainable smart cities. We need a holistic framework for the smart governance of cities by utilizing key technological drivers such as big data, Geographic Information Systems (GIS), cloud computing, Internet of Things (IoT). Geospatial Big Data applications offer predictive data science tools such as grid computing and parallel computing for efficient and fast processing to build a sustainable smart city ecosystem. Effective management of big data in storage, visualization, analytics, and analysis stages can foster green building, green energy, and net zero targets of countries. Parallel computing systems have the ability to scale up analysis on geospatial big data platforms which is key for ocean, atmosphere, land, and climate applications. In this study, it is aimed to create the necessary technical infrastructure for smart city applications with a holistic big data management approach. Thus, a smart city model framework is developed for Smart Environment and Smart Governance components and performance comparison of Dask-GeoPandas and Apache Sedona parallel processing systems are carried out. Apache Sedona performed better on the performance test during read, write, join and clustering operations.

Exact Wirelength of Embedding 3-Ary n-Cubes into Certain Cylinders and Trees

Graph embeddings play a significant role in the design and analysis of parallel algorithms. It is a mapping of the topological structure of a guest graph G into a host graph H, which is represented as a one-to-one mapping from the vertex set of the guest graph to the vertex set of the host graph. In multiprocessing systems, the interconnection networks enhance the efficient communication between the components in the system. Obtaining minimum wirelength in embedding problems is significant in the designing of networks and simulating one architecture by another. In this paper, we determine the wirelength of embedding 3-ary n-cubes into cylinders and certain trees.

SpecMap: An efficient spectral partitioning based static application mapping algorithm for 2D mesh NoCs

SummaryNetwork‐on‐chip (NoC) is adopted as a flexible and effective communication backbone by multiprocessor systems with core counts ranging from a few to hundreds. The performance of NoC based systems greatly rely on the communication between cores when two dependent tasks of an application are mapped to these cores. Hence, application mapping becomes a critical issue in NoC‐based systems as it affects the overall performance of the system. Application mapping aims to reduce the communication among the cores by carefully mapping the highly communicating tasks. Most of the existing static mapping approaches consider only single‐task platforms. In this article, we propose an efficient multi‐task static mapping algorithm called , for regular 2D NoC systems. consists of three stages namely, (i) graph partitioning, (ii) topology clustering, and (iii) mapping. In the graph partitioning stage, accurately identifies and groups the highly communicating tasks based on spectral graph partitioning. Then, the clustering and mapping stages allocate the most communicating tasks in the same or adjacent multi‐tasking cores. It also eliminates the interference between multiple applications by mapping them into different clusters of the NoC network. Simulations of have been conducted on different synthetic and real‐life applications using Gem5 simulator. The simulation results show considerable improvements for SpecMap in terms of communication cost, average network latency, energy consumption, throughput, and execution time as compared to the state‐of‐the‐art algorithms.

Implementation of Real-Time Space Target Detection and Tracking Algorithm for Space-Based Surveillance

Space-based target surveillance is important for aerospace safety. However, with the increasing complexity of the space environment, the stellar target and strong noise interference pose difficulties for space target detection. Simultaneously, it is hard to balance real-time processing with computational performance for the onboard processing platform owing to resource limitations. The heterogeneous multi-core architecture has corresponding processing capabilities, providing a hardware implementation platform with real-time and computational performance for space-based applications. This paper first developed a multi-stage joint detection and tracking model (MJDTM) for space targets in optical image sequences. This model combined an improved local contrast method and the Kalman filter to detect and track the potential targets and use differences in movement status to suppress the stellar targets. Then, a heterogeneous multi-core processing system based on a field-programmable gate array (FPGA) and digital signal processor (DSP) was established as the space-based image processing system. Finally, MJDTM was optimized and implemented on the above image processing system. The experiments conducted with simulated and actual image sequences examine the accuracy and efficiency of the MJDTM, which has a 95% detection probability while the false alarm rate is 10−4. According to the experimental results, the algorithm hardware implementation can detect targets in an image with 1024 × 1024 pixels in just 22.064 ms, which satisfies the real-time requirements of space-based surveillance.