Multi-core Platforms Research Articles

DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems

Mixed-criticality systems are promoted in industry due to their potential to reduce size, weight, power, and cost. Nonetheless, deploying mixed-criticality applications on commercial multi-core platforms remains a highly challenging problem. To name a few reasons: (i) Industrial mixed-criticality applications are usually complex reactive applications, which cannot be specified by traditional, e.g., dataflow-based, models of computation. Appropriate mixed-criticality models of computation built upon Vestal’s assumptions are missing; (ii) Scheduling such applications on multicores with shared resources, such as memory buses, requires that any timing interference among applications of different criticality is bounded in order to guarantee—the necessary for certification—temporal isolation and to enable incremental design; (iii) The implementation of isolation-preserving mixed-criticality schedulers is itself subject to certification. Hence, it needs to be not only efficient, but also provably correct. This paper proposes, for the first time, a complete design flow covering all aspects from specification, using a novel mixed-criticality aware model of computation (DOL-Critical), to correct-by-construction implementation, using the principle ‘what you verify is what you generate’ which is based on a novel variant of task automata. We demonstrate the applicability of our design flow with an industrial avionic test case on the state-of-the-art Kalray MPPA®-256.

Accelerating the Branch-and-Price Algorithm Using Machine Learning

This study presents a widely applicable approach to accelerate the computation time of the Branch-and-Price (BaP) algorithm, which is a very powerful exact method used for solving complex combinatorial problems. Existing studies indicate that the most computationally demanding element of the BaP algorithm is the pricing problem. The case-studies presented in this paper show that more than 90% of the total Central Processing Unit (CPU) processing time is consumed by solving the pricing problem. The pricing problem is repetitive in nature and it solves the same problem from scratch differing only in the input dual prices. In this study, we demonstrate how to utilize the knowledge gained from previous executions of the pricing problem to reduce the solution space of pricing problems solved in future iterations. The solution is based on an online machine learning method that is not tailor-made for a specific problem (but needs a proper problem-dependent feature selection) and uses a very fast regression model that generates negligible overhead compared to the total CPU processing time of the BaP algorithm. The method predicts a tight upper bound for the current iteration of the pricing problem while preserving the exactness of the BaP algorithm. The efficiency of the proposed approach is demonstrated by two distinct case-studies: the nurse rostering problem and the scheduling of time-division multiplexing for multi-core platforms. The experiments carried out for both case-studies using benchmark instances from the literature show a 40% and 22% average CPU time reduction for the entire BaP algorithm.

Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management

One of the biggest challenges in multicore platforms is shared cache management, especially for data-dominant applications. Two commonly used approaches for increasing shared cache utilization are cache partitioning and loop tiling. However, state-of-the-art compilers lack efficient cache partitioning and loop tiling methods for two reasons. First, cache partitioning and loop tiling are strongly coupled together, and thus addressing them separately is simply not effective. Second, cache partitioning and loop tiling must be tailored to the target shared cache architecture details and the memory characteristics of the corunning workloads. To the best of our knowledge, this is the first time that a methodology provides (1) a theoretical foundation in the above-mentioned cache management mechanisms and (2) a unified framework to orchestrate these two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by an order of magnitude keeping at the same time the number of arithmetic/addressing instructions to a minimal level. We motivate this work by showcasing that cache partitioning, loop tiling, data array layouts, shared cache architecture details (i.e., cache size and associativity), and the memory reuse patterns of the executing tasks must be addressed together as one problem, when a (near)-optimal solution is requested. To this end, we present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.

Dynamic cloud resource management for efficient media applications in mobile computing environments

Single-instruction-set architecture (Single-ISA) heterogeneous multi-core processors (HMP) are superior to Symmetric Multi-core processors in performance per watt. They are popular in many aspects of the Internet of Things, including mobile multimedia cloud computing platforms. One Single-ISA HMP integrates both fast out-of-order cores and slow simpler cores, while all cores are sharing the same ISA. The quality of service (QoS) is most important for virtual machine (VM) resource management in multimedia mobile computing, particularly in Single-ISA heterogeneous multi-core cloud computing platforms. Therefore, in this paper, we propose a dynamic cloud resource management (DCRM) policy to improve the QoS in multimedia mobile computing. DCRM dynamically and optimally partitions shared resources according to service or application requirements. Moreover, DCRM combines resource-aware VM allocation to maximize the effectiveness of the heterogeneous multi-core cloud platform. The basic idea for this performance improvement is to balance the shared resource allocations with these resources requirements. The experimental results show that DCRM behaves better in both response time and QoS, thus proving that DCRM is good at shared resource management in mobile media cloud computing.

An industrial view on the common academic understanding of mixed-criticality systems

With the rapid evolution of commercial hardware platforms, in most application domains, the industry has shown a growing interest in integrating and running independently-developed applications of different “criticalities” in the same multi-core platform, with the objective of improving the performance/cost ratio of the system. Such integrated systems are commonly referred to as mixed-criticality systems (MCS). Most of the MCS-related research published in the state-of-the-art cite the safety-related standards associated to each application domain (e.g. aeronautics, space, railway, automotive). However, those standards are not, in most cases, freely available, and do not always clearly and explicitly specify the requirements for mixed-criticality systems. This paper addresses the important challenge of presenting the relevant information available in some of the safety-related standards, such that the mixed-criticality concept is understood from an industrialist’s perspective. In addition, the paper evaluates state-of-the-art mixed-criticality real-time scheduling models and algorithms against the safety-related standards.

Optimized sparse Cholesky factorization on hybrid multicore architectures

We present techniques for supernodal sparse Cholesky factorization on a hybrid multicore platform consisting of a multicore CPU and GPU. The techniques are the subtree algorithm, pipelining and multithreading. The subtree algorithm [15] minimizes PCIe transmissions by storing an entire branch of the elimination tree in the GPU memory (the elimination tree is a tree data structure describing the workflow of the factorization), and also reduces the total kernel launch time by launching BLAS kernels in batches. The pipelining technique overlaps the execution of GPU kernels and PCIe data transfers. The multithreading technique [17] creates multiple threads for both the CPU and the GPU, to utilize concurrency of the elimination tree. Our experimental results on a platform consisting of an Intel multicore processor along with an Nvidia GPU indicate a significant improvement in performance and energy over CHOLMOD (SuiteSparse 4.5.3), a sparse algorithm, after these techniques are applied.

FID-sketch: an accurate sketch to store frequencies in data streams

Sketches are being extensively used in a large number of real world applications to estimate frequencies of data items. Due to the unprecedented increase in the amount of Internet data and a relatively slower increase in the size of on-chip memories, existing sketches are becoming increasingly unable to keep the accuracy of the frequency estimates at an acceptable level. In this paper, we design a new sketch, called FID-sketch, that has a significantly higher accuracy and a much smaller on-chip memory footprint compared to the existing sketches. The key intuition behind the design of the FID-sketch is that before inserting an item, unlike prior sketches, it first estimates the current value of the frequency of that item stored in the sketch, and then increments as few counters as possible instead of incrementing a pre-determined fixed number of counters. We carried out extensive experiments to evaluate and compare the performance of FID-sketch with existing sketches on multi-core CPU and GPU platforms. Our experimental results show that our FID-sketch significantly outperforms the state-of-the-art with 36.7 times lower relative error. We have released the source code of our proposed sketch and other related sketches that we implemented at Github [21].

Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Abstract With more functionality added to future safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core processors offer a potential that is promising, but they also suffer from two issues that are only recently being addressed in the safety-critical contexts: lack of methods for assuring timing determinism, and higher sensitivity to permanent and transient faults due to shrinking transistor sizes. This paper reviews major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. We consider the classic approach for analyzing the impact of faults in such systems, namely fault injection. The review therefore explores the area in which timing effects are studied when fault injection methods are used. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with fault tolerance techniques. We assess the applicability of the methods to currently available multi-core processors used in avionics. Dark spots on the research map of the integration problem of hardware reliability and timing predictability for multi-core avionics systems are identified.

Joint DVFS and Parallelism for Energy Efficient and Low Latency Software Video Decoding

In this paper, we aim to bridge the gap between the energy efficiency of software and hardware video decoders by combining both DVFS and parallelism. For this purpose, we, first, propose an adaptive DVFS algorithm for energy efficient mono-core decoding of H.264 videos. The proposed solution uses metadata (normalized by MPEG) providing information about the upcoming workload. These metadata are processed within an adaptive filter to build dynamically an accurate complexity model used to calculate the minimal processor frequencies for decoding video frames while guaranteeing real time constraints. Then, we generalize the proposed DVFS to slice-based multi-threaded parallel video decoders on multi-core platforms. Our performance evaluations showed that the proposed algorithm for mono-core decoding is able to converge to an accurate complexity model (4 percent) in less than 1 second. Moreover, it is simple to implement, induces very low overhead and achieves up to 46 percent energy saving as compared to the ondemand Linux DVFS governor. On the other hand, joint use of parallelism and DVFS allows 720p software video decoding with only 17 percent more energy consumption as compared to a hardware video decoder.

Multi core Commercial Off-the-Shelf (Cots) Under the implementation of fault Tolerance

The fault-tolerant design is applicable to high performance IT systems, increased by an amount of false contacts from smaller structures. As a substitute for the hardware solutions that are based on software error tolerance mechanisms, proper solution can increase the reliability for the commercial-of-the-shelf (COTS) multicore processors within a cheaper range with efficiency for further use. This paper aims to create a hybrid approach to hardware-related software, the current Core Intel x86 family and Xeon multi-core platforms. To support memory transactional hardware (TSX Intel) in creating implicit hits and fast rollback redundant process execution and signature comparison for error detection and error recovery can be done through transactional packing. Existing applications have improved redundant instrumentation performance with tolerance to post-binary compound errors. Further physical improvement increases the applicability of the CPU SPEC benchmark approach proposed in 2006 with administrative costs and rated performance over 47% on average based on the existence of proposed hardware support. In this paper, all the techniques for hardware and software level that help us for the removal of faults in multi-core commercial-of-the-shelf (COTS) and that makes the system able enough to work properly.

A method of boundary equations for unsteady hyperbolic problems in 3D

We consider interior and exterior initial boundary value problems for the three-dimensional wave (d'Alembert) equation. First, we reduce a given problem to an equivalent operator equation with respect to unknown sources defined only at the boundary of the original domain. In doing so, the Huygens' principle enables us to obtain the operator equation in a form that involves only finite and non-increasing pre-history of the solution in time. Next, we discretize the resulting boundary equation and solve it efficiently by the method of difference potentials (MDP). The overall numerical algorithm handles boundaries of general shape using regular structured grids with no deterioration of accuracy. For long simulation times it offers sub-linear complexity with respect to the grid dimension, i.e., is asymptotically cheaper than the cost of a typical explicit scheme. In addition, our algorithm allows one to share the computational cost between multiple similar problems. On multi-processor (multi-core) platforms, it benefits from what can be considered an effective parallelization in time.

Fast implementation of area integral model SART algorithm based on look-up table

Forward projection and back-projection are two computationally intense operations in simultaneous algebraic reconstruction technique (SART), especially for area integral model (AIM). We have proposed a fast forward projection algorithm for AIM-based algebraic reconstruction technique, which can be used to accelerate the forward projection operation of area integral model SART. However, the back-projection operation is extremely time-consuming due to its complexity. In this paper, we propose a fast approach to improve the reconstruction speed of AIM-based SART algorithm. To avoid repeated computation of the intersection between rays and pixels, we construct three look up tables (LUTs) to store the number of rays that intersecting with a given pixel, and the corresponding ray indices and weighting factors, respectively, which can be done during the forward projection operation. In the back-projection operation, we update pixels value using these LUTs. On this basis, we utilize the multi-threading technique to implement the forward projection and back-projection operations on a multi-core platform. Experimental results show that the proposed LUT-based approach with multi-core acceleration achieves a speedup of 36.5 times over the conventional approach, and preserves accuracy of the results.

Scheduling Parallel Real-Time Recurrent Tasks on Multicore Platforms

We consider the scheduling of a real-time application that is modeled as a collection of parallel and recurrent tasks on a multicore platform. Each task is a directed-acyclic graph (DAG) having a set of subtasks (i.e., nodes) with precedence constraints (i.e., directed edges) and must complete the execution of all its subtasks by some specified deadline. Each task generates potentially infinite number of instances where the releases of consecutive instances are separated by some minimum inter-arrival time. Each DAG task and each subtask of that DAG task is assigned a fixed priority. A two-level preemptive global fixed-priority scheduling ( GFP ) policy is proposed: a task-level scheduler first determines the highest-priority ready task and a subtask-level scheduler then selects its highest-priority subtask for execution. To our knowledge, no earlier work considers a two-level GFP scheduler to schedule recurrent DAG tasks on a multicore platform. We derive a schedulability test for our proposed two-level GFP scheduler. If this test is satisfied, then it is guaranteed that all the tasks will meet their deadlines under GFP . We show that our proposed test is not only theoretically better but also empirically performs much better than the state-of-the-art test in scheduling randomly generated parallel DAG task sets.

Scalability of a multi-physics system for forest fire spread prediction in multi-core platforms

Advances in high-performance computing have led to an improvement in modeling multi-physics systems because of the capacity to solve complex numerical systems in a reasonable time. WRF–SFIRE is a multi-physics system that couples the atmospheric model WRF and the forest fire spread model called SFIRE with the objective of considering the atmosphere–fire interactions. In systems like WRF–SFIRE, the trade-off between result accuracy and time required to deliver that result is crucial. So, in this work, we analyze the influence of WRF–SFIRE settings (grid resolutions) into the forecasts accuracy and into the execution times on multi-core platforms using OpenMP and MPI parallel programming paradigms.

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the state-of-art, in terms of performance and reliability.

Accelerating finite-rate chemical kinetics with coprocessors: Comparing vectorization methods on GPUs, MICs, and CPUs

Accurate and efficient methods for solving stiff ordinary differential equations (ODEs) are a critical component of turbulent combustion simulations with finite-rate chemistry. The ODEs governing the chemical kinetics at each mesh point are decoupled by operator-splitting allowing each to be solved concurrently. An efficient ODE solver must then take into account the available thread and instruction-level parallelism of the underlying hardware, especially on many-core coprocessors, as well as the numerical efficiency. A stiff Rosenbrock and a nonstiff Runge–Kutta ODE solver are both implemented using the single instruction, multiple thread (SIMT) and single instruction, multiple data (SIMD) paradigms within OpenCL. Both methods solve multiple ODEs concurrently within the same instruction stream. The performance of these parallel implementations was measured on three chemical kinetic models of increasing size across several multicore and many-core platforms. Two separate benchmarks were conducted to clearly determine any performance advantage offered by either method. The first benchmark measured the run-time of evaluating the right-hand-side source terms in parallel and the second benchmark integrated a series of constant-pressure, homogeneous reactors using the Rosenbrock and Runge–Kutta solvers. The right-hand-side evaluations with SIMD parallelism on the host multicore Xeon CPU and many-core Xeon Phi co-processor performed approximately three times faster than the baseline multithreaded C++ code. The SIMT parallel model on the host and Phi was 13%–35% slower than the baseline while the SIMT model on the NVIDIA Kepler GPU provided approximately the same performance as the SIMD model on the Phi. The runtimes for both ODE solvers decreased significantly with the SIMD implementations on the host CPU (2.5–2.7×) and Xeon Phi coprocessor (4.7–4.9×) compared to the baseline parallel code. The SIMT implementations on the GPU ran 1.5–1.6 times faster than the baseline multithreaded CPU code; however, this was significantly slower than the SIMD versions on the host CPU or the Xeon Phi. The performance difference between the three platforms was attributed to thread divergence caused by the adaptive step-sizes within the ODE integrators. Analysis showed that the wider vector width of the GPU incurs a higher level of divergence than the narrower Sandy Bridge or Xeon Phi. The significant performance improvement provided by the SIMD parallel strategy motivates further research into more ODE solver methods that are both SIMD-friendly and computationally efficient.

Principal Component Analysis Based Filtering for Scalable, High Precision k-NN Search

Approximate $k$ Nearest Neighbours (A $k$ NN) search is widely used in domains such as computer vision and machine learning. However, A $k$ NN search in high-dimensional datasets does not scale well on multicore platforms, due to its large memory footprint. Parallel A $k$ NN search using space subdivision for filtering helps reduce the memory footprint, but its loss of precision is unstable. In this paper, we propose a new data filtering method—PCAF—for parallel A $k$ NN search based on principal component analysis. PCAF improves on previous methods, demonstrating sustained, high scalability for a wide range of high-dimensional datasets on both Intel and AMD multicore platforms. Moreover, PCAF maintains highly precise A $k$ NN search results.

Parallelization of stochastic bounds for Markov chains on multicore and manycore platforms

The author demonstrates the methodology for parallelizing of finding stochastic bounds for Markov chains on multicore and manycore platforms. The stochastic bounds algorithm for Markov chains with the sparse matrices is investigated, thus needing a lot of irregular memory access. Its parallel implementations should scale across multiple threads and characterize with a high performance and performance portability between multicore and manycore platforms. The presented methods are built on the usage of two parallelization extensions of the C++ language: OpenMP and Cilk Plus. For this two extensions, we use two programming models, namely loop parallelism and task-based parallelism. The numerical experiments show the execution time of the implementations and the scalability on multicore and manycore platforms. This work provides the parallel implementations and at the same time presents an educational example of how computer science problems with irregular memory access can be implemented for high performance using OpenMP and Cilk Plus.

Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

Technology scaling has enabled the integration of large number of transistors into a single chip, leading to performance enhancement via incorporation of Processing Elements (PEs), Intellectual Property (IP) cores and Memory Units together on the same platform. On the downside, it has led on-chip components to be more susceptible to faults, both permanent and transient. Permanent faults are predictable in nature and can be dealt with at the time of manufacturing or in field using spares/redundancy. Transient faults also adversely affect the application performance but are unpredictable in nature. Handling transient faults is a challenging task, especially in a real-time system where different applications are executed with various timing constraints. Although significant amount of work has been reported in literature for transient fault management, it lacks addressing the temporal constraint satisfaction of the tasks while restricting the energy expenditure of the system. Existing fault tolerant policies do task replication to ensure higher percentage of deadline satisfaction but at the cost of higher energy consumption. Checkpointing approach can make energy consumption low, however, the number of tasks satisfying their timing constraint also becomes low. Thus a fault tolerant policy which could jointly address the timing and energy constraint in a real time system is desirable. This work proposes an algorithm to intelligently perform a fault-tolerant resource allocation in real-time dynamic scenarios where tasks of applications are not known apriori. The slack times of the incoming tasks have been exploited in the application mapping/scheduling phase of the algorithm, to assign a fault tolerant policy to the corresponding task for mitigating the effect of transient faults. This helps to improve the deadline satisfaction of the task and also reduce the energy consumption. While comparing with existing works, the proposed algorithm achieves 19.8%, 43.5% and 85.8% improvement in deadline satisfaction compared to MXR [1], CPR [2] and TR [3], respectively. On an average, the energy consumption is reduced by 29.1% and 6.7%, compared to AR [4] and MXR [1].

SparseX

The Sparse Matrix-Vector Multiplication (SpMV) kernel ranks among the most important and thoroughly studied linear algebra operations, as it lies at the heart of many iterative methods for the solution of sparse linear systems, and often constitutes a severe performance bottleneck. Its optimization, which is intimately associated with the data structures used to store the sparse matrix, has always been of particular interest to the applied mathematics and computer science communities and has attracted further attention since the advent of multicore architectures. In this article, we present SparseX, an open source software package for SpMV targeting multicore platforms, that employs the state-of-the-art Compressed Sparse eXtended (CSX) sparse matrix storage format to deliver high efficiency through a highly usable “BLAS-like” interface that requires limited or no tuning. Performance results indicate that our library achieves superior performance over competitive libraries on large-scale problems.