Multichip Module-deposited Research Articles

Development of MCM-D Technology with Photosensitive Benzocyclobutene

This paper evaluates and compares the development of Multi-Chip Module Deposited (MCM-D) technology using photosensitive benzocyclobutene (BCB) with the non-photosensitive BCB to fabricate passive devices. The polymer was used to isolate the metal/interconnection layers and also as the dielectric for the capacitors. Ni-P/Au was used as the conductor film and Ta2N as the resistor film. The resistors’ sheet resistance was measured with both transfer length method (TLM) and direct measurement while the measurements of the capacitors and inductors required the use of a Vector Network Analyzer (VNA) and some mathematical algorithms.

Evaluating the influence of MCM-D post-processing on silicon microstrip sensors

Silicon micro-strip modules are traditionally built as a composite object of sensors, front-end ASICs, electronics hybrid, pitch adapters and passive components. This paper reports on a novel approach to use Multi-chip Module-Deposited (MCM-D) technology to build the electronics hybrid and pitch adapter directly on the silicon sensor, by post-processing the sensor wafers. A first prototype was made to evaluate the influence of the post-processing on the sensors in terms of the electrical performance, mechanical stability and the radiation hardness. The processing was done on a wafer with miniature strip sensors and featured one dielectric layer, one metal layer and one passivation layer. This paper summarises the results from this prototype run. It reports on the sensor leakage current, strip capacitance, inter-strip resistance and charge collection efficiency. These measurements are done on non-irradiated devices and devices subjected to proton irradiation. Furthermore it reports on the mechanical integrity of the post-processed assembly.

Slot coupled patch antenna in MCM-D for millimeter wave detector matrix applications

In this work we assess the feasibility of fabricating a matrix of antennas for the millimeter (mm)-wave band using the “Multi Chip Module – Deposited (MCM-D)” process. The main focus of the design is to minimize the cross coupling between the antennas fabricated on the common substrate. We investigate the use of a virtual cavity formed by metalized vias in order to reduce the cross coupling to the neighboring cells. The radiation efficiency is analyzed in detail, and experimental results of a 2 × 2 array are presented.

Integrated 79 GHz UWB automotive radar front-end based on Hi-Mission MCM-D silicon platform

A highly integrated silicon platform (Hi-Mission) for high frequency applications is introduced. This platform utilizes heterogeneous Multi-Chip Module-Deposited (MCM-D) technology with integrated passive devices together with silicon and GaAs Monolithic Microwave Integrated Circuit (MMIC) technology developed for the automotive Ultra Wide Band (UWB) radar (short-range radar) frequency band from 77 to 81 GHz. Developments are described in the area of MCM-D process development, MMIC, integrated phased array antenna, module design, and assembly process development. The demonstrator is composed of two test vehicles designed for conducted and radiated measurements, respectively. Test results are presented at the component and module level.

Integration of Ta–N Thin Film Resistors on Anodic Alumina MCM-D Substrate

The aim of this work is to evaluate the changes in microstructures and electrical properties of a tantalum nitride (Ta–N) thin film integrated on an aluminum anodization multichip module deposited (MCM-D) substrate. A Ta–N resistor with a thickness of 100 nm was integrated at the bottom layer of the MCM-D substrate using rf reactive sputtering. Effects of aluminum anodization process on the Ta–N thin film resistor were studied. The results show that the oxide bulges composed of Ta2O5 and Ta–O–N are formed at the Ta–N film surface due to the effect of the upper layer of porous anodic alumina. The resistivity and the temperature coefficient of resistance of the Ta–N resistor remain unchanged. The integrated resistor is more stable owing to the protection of the oxide bulges.

Embedded Decoupling Capacitors up to 80 nF on Multichip Module-Deposited with Quasi-Three-Dimensional Metal–Insulator–Metal Structure

Embedded capacitors with available capacitances up to ∼80 nF have been implemented on a thin-film multichip module-deposited (MCM-D) substrate. By cost-effective silicon wet etching, a new metal–insulator–metal (MIM) structure named quasi-three-dimensional MIM capacitor has been realized. The groove structure formed by silicon wet etching increases effective capacitance area, thus enhancing capacitance density by 1.5 times. No additional mask or process step is required to form the groove structure since it is simultaneously patterned and etched with ground bumps that are for effective interconnection. The implemented capacitors have capacitances from 2 to 78 nF with a scalable density of 3.6 nF/mm2, indicating that they are excellent candidates for high-power decoupling application.

Analysis and Design of Planar, Spiral-Shaped, Transmission-Line Transformers

Coupled microstrip line theory is applied to analyze planar Ruthroff transmission-line transformers (TLTs). The results demonstrate that the TLT's low frequency response improves as the microstrip line's even-mode impedance increases, whereas the ratio of load impedance to the line's odd-mode impedance controls the high frequency response. Analysis of an approximate model of coupled microstrip lines formed into a spiral leads to a technique for predicting the performance of planar, spiral-shaped, Ruthroff TLTs. Microwave measurements up to 10 GHz are compared with predictions from the model for regular and suspended Ruthroff TLTs fabricated through a multichip-module deposited (MCM-D) process

Studies on MCM-D pixel-detector-modules

In the context of the development of the ATLAS-Pixel-Detector [1], a technology for building up the high density interconnects has been studied, the MCM-D (multi chip module deposited) technology. Results of building up first assemblies have been reported in [2]. MCM-D technology allows to build up assemblies with uniformly segmented sensors. Especially the use of 'equal-sized(-bricked)' sensor geometry has been studied.

Multi Chip Modules technologies

In the past few years, impressive progresses in electronic devices and their packaging have been achieved. High energy physicists benefit from this, being able to minimise the amount of material in their Vertex-Detectors. Although the environment of Vertex-Detectors is much more controlled and stabilised than in the industry- or end-user-applications, the requirements of material-budget and device complexity are higher. This paper tries to give a short overview of the existing Multi Chip Module technologies used in Vertex-Detectors and focuses on the prototyping results of an upcoming Multi Chip Module technology, called Multi Chip Module-Deposited (MCM-D), as it is planned to be used for the innermost part of the ATLAS Pixel detector.

Low-cost large area processing using small area substrates-a novel multitiled palletization concept for MCM-D thin film process

Multichip module-deposited (MCM-D) has been the solution for integrated high density packaging due to its superior line resolution and higher inputs/outputs (I/O) density compared to MCM-C and multichip module-laminate (MCM-L) technologies. However the consumer demand for high performance products at reduced costs is ever increasing, and this trend is expected to continue in the 21st Century. In order to find a low-cost solution for future MCM-D packaging, a novel palletization process which incorporates several tiles (alumina or silicon) on a large carrier glass (pallet) has been established in this study. The multitiling format provides simultaneous processing of several small tiles onto a re-usable CTE matched carrier glass. The tiles are attached to the glass with a low modulus adhesive that can be released at an elevated temperature (/spl sim/450/spl deg/C). The objective of this study is to develop a multitiling process for a 300 mm/spl times/300 mm area that is scalable up to 600 mm/spl times/600 mm format. There are several challenges in realization of the large area palletization approach, such as formulation and qualification of a high temperature reworkable adhesive and minimization of out-of-plane warpage of the tiled assembly. Finite element models for warpage and its validation by shadow moire measurement, formulation of a compliant adhesive for thermal stability up to 400/spl deg/C are reported in previous publications. This paper deals with (1) the validation of the palletization concept on a 300 mm x 300 mm glass with weight restriction below 3 lbs and thickness limitation to <6.25 mm, and (2) qualification of the formulated adhesive through a correlative study on high temperature detachability of the attached tiles, chemical compatibility of the adhesive with acids, bases, and less polar solvents, and interfacial shear strength at the lass/adhesive/tile joints. MCM-D thin film process on the tiled substrates is to be conducted by the member companies of the MCM-D Consortium.

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip.

Fabrication of a Fully Integrated Passive Module for Filter Application Using MCM-D Compatible Processes

Integral passive is an emerging technology which is currently perceived as a possible alternative to the discrete passive technology in fulfilling the next generation packaging needs. Although discrete surface mount passive components (resistors, capacitors, and inductors) have been well characterized, the development of integral passive components suitable for co-integration on the board level is relatively recent. Since in some applications the number of passive components can exceed the number and the area of IC chips on a circuit board or in a package, such integration of passive components would be necessary to substantially eliminate part count and reduce device area. To address these issues, integration technology for passive elements in the same manner as for transistors is necessary. In addition, the fabrication sequence of all integral passive components should be mutually compatible for co-integration on the same substrate. In this paper, materials and fabrication issues for passive elements such as resistors (R), capacitors (C), and inductors (L) and the feasibility of integration of these fabricated passive components on glass substrates have been addressed. An active filter circuit has been selected for a case study for R, L, and C co-integration. This passive module contains eleven resistors, four capacitors, and four inductors, and is fabricated using MCM-D (multichip module-deposited) compatible processes. A variety of materials appropriate for fabrication of integral passives in a mutually compatible fashion were investigated, including chromium and nickel-chromium resistors, composites of high dielectric constant materials in epoxies for capacitor dielectrics, and composites of magnetic ferrite particles in polyimides for inductor core and shielding. The fabricated devices showed good agreement between the design values and the corresponding measured values. It is anticipated that some of these materials and fabrication processes can be implemented for the MCM-L (multichip module-laminate) compatible packaging. © 2000 Kluwer Academic Publishers

A Study on Warpage of Flexible SS Substrates for Large Area MCM-D Packaging

This paper presents potential application of stainless steel (SS) as a base substrate material for large area multi-chip module-deposited (MCM-D) packaging. Preliminary results on via formation on SS substrates by laser drilling, dielectric coating on SS surface and on via sidewall, via filling for front-to-back interconnects, and subsequent curing of via filling material are reported in this paper. The objective of this DARPA funded MCM-D Consortium is to investigate the feasibility of application of stainless steel materials for large area MCM-D packaging through laboratory prototypes and simulated thin film process. This paper particularly addresses the warpage issues related to via formation, dielectric coating on the substrates, and via filling process after substrates were exposed to temperatures above 130 °C for two hours. The change in process induced warpage was quantified by the simple non-destructive Shadow Moire´ technique. The end objective of this work is to be able to fabricate large area 24 in.×24 in.SS substrates with minimum warpage. The study shows that SS can be a candidate substrate for large area MCM-D packaging. [S1043-7398(00)00702-7]

Laser formed metallic connections

Solid metallic connections have been successfully formed between two standard levels of metallization using a focused infrared (IR) laser. This new process of laser formed connections has been used to link continuous chains and with resistances of less than 0.8 /spl Omega/ per connection. A commercial laser repair system used extensively by the memory industry was employed to perform approximately 50000 individual links without failure. The electromigration resistance is comparable to standard metal interconnect. This technology has the potential to replace laser fuse cutting techniques to implement repair schemes and it can be used to program wiring in multichip module-deposited (MCM-D) or wafer scale integration applications implemented on silicon substrates. Furthermore, because it is an additive process, it lends itself to redundancy for higher yield and reliability.

Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits

Various micromachining techniques exist to realize integrated microelectromechanical systems (MEMS), which include sensors, signal processing and/or driving circuits, and/or actuators in one small die. Post-processing techniques performed on foundry-fabricated circuits (e.g., MOSIS) are attractive since such an approach eliminates the need for an in-house integrated circuit fabrication line to produce integrated MEMS. A method based on the combination of metallic (e.g., electroplating) micromachining techniques with multichip module deposited (MCM-D) processes is a possible candidate to realize vertically-stacked integrated MEMS using the post-processing of integrated circuits (post-IC) approach. In order to realize such devices, planarization of the surface of foundry-fabricated circuit chips or wafers is often required. In such planarization layers, mechanical and chemical stability, as well as adhesion between the circuit-containing substrate and the micromachined devices, should be addressed. A PI/BCB/PI sandwich interlayer system, which utilizes both advantages of DuPont polyimide PI 2611 and Dow benzocyclobutene (BCB) Cyclotene 3022 series, was developed as a planarization interlayer for vertically integrated MEMS. The PI/BCB/PI interlayer system shows an over 95% degree of planarization (DOP) as well as passes the Method 107G Thermal Shock from the military standard MIL-STD-202F. A interlayer system was also developed as an alternative to the PI/BCB/PI system.

Design for packageability-early consideration of packaging from a VLSI designer's viewpoint

Designing VLSI dies without considering packaging issues may result in a suboptimum system. It is argued that before the design of VLSI dies is completed, packaging issues should be evaluated, since they may affect choices in VLSI circuit design and layout. To illustrate this, the design of an image processing chip-set of three integrated circuits for wire-bond printed circuit board (PCB) and flip-chip multichip module deposited (MCM-D) technologies is reviewed. It is shown that the characteristics of these chips vary, since they are designed with different packaging in mind. >