Multi-bit Quantizer Research Articles

On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization

Continuous-time (CT) sigma-delta (/spl Sigma//spl Delta/) modulators are growing increasingly popular in wide-band analog-digital conversion. High orders of quantization noise shaping, and multibit quantizers, are used to compensate for the low oversampling ratios in wide-band applications. These, however, add circuit complexities and excess loop delay that are detrimental to the /spl Sigma//spl Delta/ control loop. This paper presents an exact mathematical analysis technique, based on the CT-discrete time equivalence, that can take these effects into account. A design-by-optimization approach based on that analysis is used to compensate for these effects, avoid intractability issues and to gain flexibility in the design. It is also shown that it is advantageous not to fix the position of the quantization noise-shaping zeros in the signal band.

Study of nonlinear phenomena in a multi-bit bandpass sigma delta modulator

Bandpass sigma delta modulators (SDMs) have applications in areas such as digital radio demodulation. It is well known that bandpass SDMs with single bit quantizers can exhibit nonlinear and complex state space dynamics like elliptical fractal patterns. These fractal patterns are usually confined in trapezoidal regions. In this paper, we consider bandpass SDMs with multi-bit quantizers. Their nonlinear dynamics is studied.

A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of /spl Sigma//spl Delta/ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit /spl Sigma//spl Delta/ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area.

OCCURRENCE OF ELLIPTICAL FRACTAL PATTERNS IN MULTI-BIT BANDPASS SIGMA DELTA MODULATORS

It has been established that the class of bandpass sigma delta modulators (SDMs) with single bit quantizers could exhibit state space dynamics represented by elliptic or fractal patterns confined within trapezoidal regions. In this letter, we find that elliptical fractal patterns may also occur in bandpass SDMs with multibit quantizers, even for the case when the saturation regions of the multibit quantizers are not activated and a large number of bits are used for the implementation of the quantizers. Moreover, the fractal pattern may occur for low bit quantizers, and the visual appearance of the phase portraits between the infinite state machine and the finite state machine with high bit quantizers is different. These phenomena are different from those previously reported for the digital filter with two's complement arithmetic. Furthermore, some interesting phenomena are found. A bit change of the quantizer can result in a dramatic change in the fractal patterns. When the trajectories of the corresponding linear systems converge to a fixed point, the regions of the elliptical fractal patterns diminish in size as the number of bits of the quantizers increases.

A novel noise efficient feedback DAC within a switched capacitor /spl Sigma//spl Delta/ ADC

Efficient sampling of the reference noise within a bilinear switched capacitor /spl Sigma//spl Delta/ analog-to-digital converter (ADC), resulting in improved thermal noise performance is presented. Bilinear integrators contain a zero at the Nyquist frequency, with the result that no charge is transferred from the reference when a transition occurs in the modulator output. The average noise power added by the reference digital-to-analog converter (DAC) can be reduced substantially if the reference DAC is sampled only when charge is to be transferred. For midscale inputs, the sampled noise from a single bit reference DAC is reduced by more than 5 dB. When multibit quantization and feedback is used the reference noise can be further suppressed, in the case of 5 bits of feedback the reference noise is reduced by more than 20 dB.

Systematic Design Exploration of Delta-Sigma ADCs

An algorithm for architecture-level exploration of the /spl Delta//spl Sigma/ A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well.

A Second Order Multi-Bit Sigma Delta Modulator with Single-Bit Feedback

Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 μm CMOS process, achieving 82 dB dynamic range at OSR e 128 and a peak SNDR of 73.1 dB.

An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters

/spl Sigma//spl Delta/-modulation is a proven method to realize high- and very high-resolution analog-to-digital converters. A particularly efficient way to implement such a modulator uses double-sampling where the circuit operates during both clock phases of the master-clock. Hence, the sampling frequency is twice the master-clock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an in-depth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of single-bit and multibit modulators are discussed.

Multirate single-bit ΣΔ modulators

It has been shown that a multibit /spl Sigma//spl Delta/ modulator can be built replacing the multibit quantizer in the forward path by a single-bit one, operating at a higher frequency, by an increase in the oversampling ratio of the last integrators of the loop. An improved topology is proposed here which obtains similar performances with single-bit feedback, overcoming drawbacks inherent to high resolution digital to analog converters.

Multirate ΣΔ modulators

New high-speed /spl Sigma//spl Delta/ analog to digital converters (ADCs) are required for xDSL and RF receivers. As sampling frequency is upper limited by the amplifier bandwidth and power consumption, these high-speed, low-power converters operate with a small oversampling ratio. Usually, they are high-order cascade structures with a multibit quantizer in the last stage. All these approaches use a unique sampling frequency. This paper shows that multirating is a useful technique to reduce power consumption in high speed /spl Sigma//spl Delta/ modulators. To this end, two different multirate /spl Sigma//spl Delta/ modulators are proposed. The first one uses a low sampling frequency in the first integrator(s) of a single loop structure, while the second one uses a low oversampling frequency in the first stage(s) of a cascade converter.

Nonlinear Quantization in Low Oversampling Ratio Sigma-Delta Noise Shapers for RF Applications

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low oversampling ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low oversampling ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters

Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta-sigma data converters because they facilitate delta-sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in delta-sigma analog-to-digital converters the mismatch-shaping logic is in the feedback path of the delta-sigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatch-shaping logic. This paper presents and analyzes several variations of the switching blocks within a tree-structured mismatch-shaping DAC that result in the most hardware-efficient first-order and second-order mismatch-shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagation-delay reduction so as to tailor designs to specific applications.

A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs

A multibit /spl Delta//spl Sigma/ analog-to-digital converter can achieve high resolution with a lower order modulator and lower oversampling ratio than a single-bit design. However, in a multihit /spl Delta//spl Sigma/ modulator, quantization level errors in the internal multibit quantizer can limit the /spl Delta//spl Sigma/ modulator's signal-to-noise-and-distortion and spurious-free dynamic range. For a CMOS /spl Delta//spl Sigma/ analog-to-digital converter using a flash analog-to-digital converter as its internal quantizer, comparator input offset errors are a significant source of quantization level errors. This paper presents a dynamic element matching (DEM) technique, comparator offset DEM, that modulates the sign of the comparator input offsets with a random sequence and causes the offset errors to appear as white noise and attenuated spurious tones. Measured performance of a prototype /spl Delta//spl Sigma/ modulator IC shows that comparator offset DEM enables it to achieve 98-dB peak signal-to-noise-and-distortion and 105-dB spurious-free dynamic range. Analysis and simulation of comparator offset DEM in a flash analog-to-digital converter with a periodic input and uniform dither give insight into its operation and quantify the spur attenuation it provides.

Time-referenced single-path multi-bit ΔΣ ADC using a VCO-based quantizer

In this paper, we present a single-path multi-bit delta-sigma analog-to-digital converter (/spl Delta//spl Sigma/ ADC) architecture that uses time as a reference for performing multi-bit digital-to-analog conversion in the feedback path. The architecture uses a voltage-controlled oscillator as a multi-bit quantizer. In the feedback path of the /spl Delta//spl Sigma/ ADC, the errors due to component mismatch are avoided by using a single-path for all the levels in a multi-bit digital-to-analog converter (DAC). The technique eliminates the need for feedback DAC architectures with static and dynamic component matching.

Time-domain thermal noise simulation of switched capacitor circuits and delta-sigma modulators

This paper presents an accurate and efficient algorithm for simulating the effects of thermal noise in time-domain. The algorithm presented in this paper is based on Monte Carlo methods and is applicable to linear time invariant circuits. In addition to linear time invariant elements, the algorithm can easily be extended to include clock controlled switches and single or multibit quantizers. This expands the thermal noise analysis capability to switched capacitor circuits and oversampled delta-sigma modulators. Thermal noise generated by different elements is modeled, in the time-domain, by a random pulse waveform having a desired power spectral density. Typically the noise power level is much smaller than that of other desired signals in the circuit and accurate simulation is needed to obtain correct results. In addition, random noise waveforms require the computation of many time points in each transient analysis and efficient simulation methods are needed. In this paper, a new method for computing the transient response of linear time invariant circuits is used. This method accurately and efficiently computes the response to the random pulse waveforms. In addition to thermal noise, the method can also be used to simulate the effect of random dither signals in delta-sigma modulators. Examples of noise simulation are given and, when possible, comparison with measurements, previously published results, or analytical expressions is done.

The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer

This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2/sup bq/-2)fos<fvm< (2/sup bq/-1) fos and a bq-bit counter is used, a multibit (bq-bit) quantizer can be realized, where fos is the oversampling frequency. The performance of the proposed converter is evaluated using a functional simulation. A 59-dB SNR at a 5-MHz bandwidth is obtained with fos=400 MHz, even in the case of a 1-bit quantizer. The multibit quantizer using a high frequency VCO significantly improves an SNR and signal bandwidth. This architecture is highly suitable for implementation with deep sub-/spl mu/m CMOS devices, which can attain improved switching speeds and reduce power dissipation during low voltage operation. It provides wideband oversampling ADC for video and wireless signals and a low voltage system-on-a-chip solution for multimedia applications.

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-/spl mu/m /spl Sigma//spl Delta/ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators-referred to as a 2-1-1/sub mb/ architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2.1.1/sub single-bit/ modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.

Sigma-delta ADC with reduced sample rate multibit quantizer

Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.

Delta-sigma A/D converters: The next generation

Delta-sigma A/D converters are well suited for applications requiring high resolution in a relatively low frequency bandwidth. As the technology continues to mature, the next generation of delta-sigma A/D converters will be exploited for applications requiring both high resolution and high speed. This paper describe three approaches to extending the useful bandwidth of the delta-sigma A/D converter. They include the use of multibit quantization with feedforward digital compensation, multibit quantization with feedback dynamic element matching and the use of parallelism.

Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (/spl Delta//spl Sigma/) modulators are reviewed, and a mismatch-shaping technique for bandpass /spl Delta//spl Sigma/ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time /spl Delta//spl Sigma/ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques.