Multi-bit Quantizer Research Articles

A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based $\Sigma \Delta$ Modulator

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm2.

Cooperative Information Aggregation for Distributed Estimation in Wireless Sensor Networks

The performance of distributed estimation in wireless sensor networks (WSNs) is affected by observation noise, communication errors and the noise caused by the inevitable quantization process. Reducing the number of transmitted bits per node can minimize the energy consumption and communication load, thereby prolonging the network lifetime. However, reducing the number of transmitted bits has a significant impact on the estimation performance. In this work, we propose cooperative information aggregation (CIA) approaches for distributed estimation that consider the above-mentioned issues jointly. Under the proposed schemes, a multi-bit quantizer is used to generate the local observation codeword at each node. Then, each node only transmits one predesigned bit of the derived codeword to the fusion center (FC). At the FC, the information bits transmitted cooperatively by all nodes are aggregated and fused to obtain the estimation result. We design two estimators: an aggregation hard decision estimator (AHDE) and an aggregation maximum-likelihood estimator (AMLE). Predetermining the transmitted bit at each node is formulated as a constrained optimization problem for resource allocation and the corresponding suboptimal resource allocation policies are proposed. The simulation results demonstrate that the proposed schemes can overcome the impact of observation noise and communication errors effectively.

A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm$^{2}$ 65 nm CMOS Circuit

This work presents an area- and power-efficient realization of a new time-encoding oversampling converter (TEOC) consisting of a third-order continuous time (CT) loop filter and a self-oscillating pulse-width modulator (PWM). The modulator displays similar performance to that of a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The time-encoding quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to overcome design issues in a 1.0 V supply-voltage 65 nm digital CMOS technology. The TEQ allows an exchange of amplitude-resolution by time-resolution. The approach of time-resolution alleviates the scaling difficulties of mixed-signal circuits in nano-scale technologies. The TEOC features a 63 dB dynamic-range and a peak-SNDR of 61 dB over a 20 MHz signal bandwidth. Clocked at 2.5 GHz, the complete ADC consumes 7 mW from a single 1.0 V supply, including also the reference buffers. The ADC core results in an attractively small area of 0.08 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and in a figure-of-merit (FoM=Pwr/2 · BW · 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ENOB</sup> ) of 0.17 pJ/conversion-step.

A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element

A third-order CT ΔΣ ADC that replaces the multi-bit quantizer and feedback DAC by a pulsewidth modulation (PWM) generator and time-to-digital converter (TDC) is implemented in 65 nm CMOS technology. The TDC provides a 50-level binary output code and a time-quantized feedback pulse to the modulator. It is shown that the TDC can achieve 11 bit linearity in time steps without calibration or dynamic element matching. The modulator achieves 68 dB DR in 20 MHz BW, consumes 10.5 m W and occupies 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

A wideband high-resolution time-interleaved sigma-delta modulator with VCO-based quantizer

A time-interleaved sigma-delta modulator with VCO-based quantizer for next generation wireless applications is presented. This proposed modulator firstly introduces the VCO-based multibit quantizer into the time-interleaved sigma-delta modulator, which can achieve the improvement of the signal bandwidth and signal-to-noise ratio simultaneously. Moreover, these performance metrics have no adverse effects on power consumption, which is more suitable for wireless applications. A two-channel proposed modulator is taken as an example, and the simulation results show that the proposed modulator achieves a signal-to-noise ratio of 112.1dB over a 4.7MHz signal bandwidth with a clock frequency of 300MHz, which improves 100% in the range of signal bandwidth and 21dB in the signal-to-noise ratio compared to the conventional sigma-delta modulator with the same clock frequency and power consumption.

A 9‐mW Continuous‐time Hybrid Active–Passive ΣΔ Modulator with 84‐dB Dynamic Range

AbstractA hybrid active–passive, continuous time (CT) sigma–delta (ΣΔ) modulator with a multibit quantizer is presented. The modulator is designed as a fifth‐order, dual‐loop architecture, allowing for a maximum quantizer delay of half a clock period. By removing the summing block before the quantizer as well as by introducing an active–passive hybrid loop filter, the design achieves high signal‐to‐noise ratio (SNR) comparable to a fourth‐order active design while dissipating power equivalent to a third‐order implementation. A data‐weighted averaging (DWA) algorithm implemented with analog reference shuffling is utilized to suppress the mismatches in the current‐steering digital‐to‐analog conversion (DAC) with no extra delay introduced between the quantizer and DAC. The chip, manufactured in a 1.8‐V, 0.18‐µm complementary metal oxide semiconductor (CMOS) process, experimentally achieves 79.5 dB peak SNR, 78 dB peak signal‐to‐noise‐and‐distortion ratio (SNDR), and 84‐dB dynamic range over a 1‐MHz signal bandwidth. The 0.43‐mm2 test chip consumes 9‐mW of power when clocked at 128 MHz. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley &amp; Sons, Inc.

Spectral Analysis of Pulsewidth-Modulated Sampled Signals

Pulsewidth (PW) modulation has been widely used to convert analog (or multibit digital) signals to binary streams. It is well known that PW modulation of a sampled signal produces harmonic distortion. This effect is analyzed, and new expressions are obtained for the Fourier transform of the modulated output, which are valid for any input signal. In addition, simple expressions are given to compute the harmonic distortion factors for a sinusoidal input signal. It is also shown that a three-level PW modulation can reduce the distortion factors down to a level appropriate for most signal-processing applications. Finally, these analytical results are validated by simulation for two data converters based on sigma-delta modulation, where the sampled output of a multibit quantizer is PW modulated: one digital-to-analog and one analog-to-digital converter, respectively.

An 18-bit high performance audio σ-Δ D/A converter

A multi-bit quantized high performance sigma-delta (σ-Δ) audio DAC is presented. Compared to its single-bit counterpart, the multi-bit quantization offers many advantages, such as simpler σ-Δ modulator circuit, lower clock frequency and smaller spurious tones. With the data weighted average (DWA) mismatch shaping algorithm, element mismatch errors induced by multi-bit quantization can be pushed out of the signal band, hence the noise floor inside the signal band is greatly lowered. To cope with the crosstalk between digital and analog circuits, every analog component is surrounded by a guard ring, which is an innovative attempt. The 18-bit DAC with the above techniques, which is implemented in a 0.18 μm mixed-signal CMOS process, occupies a core area of 1.86 mm2. The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB, respectively.

On the limits of communication with low-precision analog-to-digital conversion at the receiver

As communication systems scale up in speed and bandwidth, the cost and power consumption of high-precision (e.g., 8-12 bits) analog-to-digital conversion (ADC) becomes the limiting factor in modern transceiver architectures based on digital signal processing. In this work, we explore the impact of lowering the precision of the ADC on the performance of the communication link. Specifically, we evaluate the communication limits imposed by low-precision ADC (e.g., 1-3 bits) for transmission over the real discrete-time additive white Gaussian noise (AWGN) channel, under an average power constraint on the input. For an ADC with K quantization bins (i.e., a precision of log2 K bits), we show that the input distribution need not have any more than K+1 mass points to achieve the channel capacity. For 2-bin (1-bit) symmetric quantization, this result is tightened to show that binary antipodal signaling is optimum for any signal-to- noise ratio (SNR). For multi-bit quantization, a dual formulation of the channel capacity problem is used to obtain tight upper bounds on the capacity. The cutting-plane algorithm is employed to compute the capacity numerically, and the results obtained are used to make the following encouraging observations : (a) up to a moderately high SNR of 20 dB, 2-3 bit quantization results in only 10-20% reduction of spectral efficiency compared to unquantized observations, (b) standard equiprobable pulse amplitude modulated input with quantizer thresholds set to implement maximum likelihood hard decisions is asymptotically optimum at high SNR, and works well at low to moderate SNRs as well.

A Novel Cluster-Based Cooperative Spectrum Sensing with Double Adaptive Energy Thresholds and Multi-Bit Local Decision in Cognitive Radio

The cognitive radio (CR) technique is a useful tool for improving spectrum utilization by detecting and using the vacant spectrum bands in which cooperative spectrum sensing is a key element, while avoiding interfering with the primary user. In this paper, we propose a novel cluster-based cooperative spectrum sensing scheme in cognitive radio with two solutions for the purpose of improving in sensing performance. First, for the cluster header, we use the double adaptive energy thresholds and a multi-bit quantization with different quantization interval for improving the cluster performance. Second, in the common receiver, the weighed HALF-voting rule will be applied to achieve a better combination of all cluster decisions into a global decision.

A 0.7-V 870-$\mu$W Digital-Audio CMOS Sigma-Delta Modulator

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mum CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 muW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.

New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma-delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.

Comments on "Efficient multibit quantization in continuous-time Sigma Delta modulators"

The authors propose three different types of continuous-time modulators to reduce the number of comparators in the main quantizer. Employing an auxiliary quantizer helps to reduce the integrator swing range in front of the main quantizer and to decrease the number of comparators. We wish to remind that the use of the auxiliary quantizer to minimize the number of comparators was published earlier and further implemented in silicon

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

Top-down design methodology of a multi-bit continuous-time delta–sigma modulator

Transistor-level simulation of complex systems involving analog and digital parts is a time-consuming task. The growing interaction of analog and digital devices calls for the use of top-down design methodologies, resulting in behavioral modeling at different levels of abstraction. In this article, an advanced design methodology using a combination of behavioral models and transistor-level models is presented. This methodology is very interesting for complex mixed-signal IC design, improving the design flexibility and reducing the simulation time. To validate the proposed methodology, a continuous-time delta---sigma modulator based on a high-speed low-resolution quantizer is modeled, taking into account their nonidealities such as excess loop delay, clock jitter and feedback DAC element mismatch. The main features of the multi-bit quantizer are 3-bit resolution with 4 GHz sampling rate and FOM of about 7 pJ/conv. This modulator samples signals at high-IF, performing directly the analog-to-digital conversion in the modern RF front-end receivers.

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8---2 GHz bandwidth.

Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta–Sigma Modulators

We analyze the effect of nonlinearity in the first integrator of a single-loop multibit continuous-time delta-sigma modulator, when the loop filter is of the cascade of integrators with feedforward kind. When a multibit quantizer is used in the loop, we show that integrator nonlinearity results in an increased in-band noise (IBN) floor. We develop analytical relations for the IBN spectral density for several opamp topologies, assuming that the shaped quantization noise is approximately Gaussian. Our results agree well with macromodel and transistor level simulations.

A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.

Efficient Multibit Quantization in Continuous-Time &lt;formula formulatype="inline"&gt; &lt;tex&gt;$\Sigma \Delta$&lt;/tex&gt;&lt;/formula&gt; Modulators

A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer