Multi-bit ΔΣ Modulator Research Articles

A new17-bit 105.5-dB dynamic range 2-1 cascaded SAR-based [formula omitted] modulator using single-bit DAC for audio applications

A new multi-bit ΔΣ modulator using a single-bit DAC based on an improved successive approximation register (SAR) quantizer is presented. Therefore, it eliminates the requirement for a dynamic element matching circuit that is used in the conventional multi-bit ΔΣ modulators. Although the improved SAR quantizer uses a single-bit DAC to generate multi-bit outputs, the conversion time is the same in the proposed quantizer and the conventional SAR ADCs. Utilizing a single-bit DAC also reduces the number of capacitors in the modulator structure which results in reducing the power and area consumption. In addition, the proposed quantizer uses the feedback DAC of the modulator to predict the output of the integrator, which results in elimination of the internal DAC of the SAR quantizer. To study the performance of the proposed method, a 2-1 cascaded discrete-time delta sigma modulator with 4-bit proposed quantizer is designed in 180 nm CMOS technology. The proposed SAR quantizer predicts its input signal in six clock pulses. The simulation results show an SNDR of 98.94 dB and dynamic range of 105.5 dB. The proposed modulator achieves FOM of 0.2pJ/conv.-step and effective number of bit of 17bits with an input bandwidth of 20 KHz.

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.

ΔΣ digital‐RF transmitter with reduced LO leakage using segmented butterfly shufflers

Presented is a digital-RF transmitter using multi-bit ΔΣ modulators with noise-shaped segmentation and butterfly shufflers for shaping mismatches between digital-to-RF converter (DRFC) cells. The segmented butterfly shufflers prevent mismatch errors of DRFCs from aggravating the linearity and the LO leakage of the transmitter. A prototype based on a digitally-intensive top-down design is fabricated in 90 nm CMOS process. Measurement results for wideband-code division multiple access demonstrate an adjacent channel leakage ratio (ACLR) (5 MHz/10 MHz) of -49.6 dBc/-53.9 dBc and an Error Vector Magnitude of 1.89% with a main channel output power of -0.1 dBm centred at 1.95 GHz.

An 11 mW 79 dB DR ΔΣ modulator for ADSL applications

This paper shows the design of a second-order multi-bit ΔΣ modulator with hybrid structure for ADSL applications. A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed of OTAs, comparators and the DEM block. The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder. The chip is designed and fabricated in UMC 0.18 μm CMOS technology. Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz, the modulator can achieve 79 dB dynamic range, 71.3 dB SNDR, 11 mW power consumption from a 1.8 V power supply. The FOM is 1.47 pJ/step.

Two-step quantization in multibit ΔΣ modulators

An architecture to simplify the circuit implementation of the internal analog-to-digital (A/D) converter in a /spl Delta//spl Sigma/ modulator is proposed. The architecture is based on dividing the A/D conversion into two time steps, which makes the internal quantization feasible with much higher resolution than with conventional solutions. Furthermore, the time steps are interleaved so that the resolution improvement is achieved without sacrificing the speed. It is shown, with a linearized model, that the order of the noise shaping is increased by one with respect to the coarse quantization error made during the first step. For a high oversampling ratio, the coarse quantization error made in the first step is easily suppressed to an insignificant level due to the one order higher noise shaping. Depending on the partitioning of the bits between the conversion steps, the coarse error will dominate below a certain oversampling ratio. However, it is shown that the technique can be extended to more than one order higher noise shaping, making it useful for low oversampling ratios as well.