An 11 mW 79 dB DR ΔΣ modulator for ADSL applications

Abstract

This paper shows the design of a second-order multi-bit ΔΣ modulator with hybrid structure for ADSL applications. A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed of OTAs, comparators and the DEM block. The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder. The chip is designed and fabricated in UMC 0.18 μm CMOS technology. Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz, the modulator can achieve 79 dB dynamic range, 71.3 dB SNDR, 11 mW power consumption from a 1.8 V power supply. The FOM is 1.47 pJ/step.