MuGFET Simulation Tool Research Articles

Channel Length-Based Comparative Analysis of Temperature and Electrical Characteristics for SiNWT and GeNWT

This paper investigates the temperature sensitivity and electrical characteristics of Silicon Nanowire Transistor (SiNWT) and Germanium Nanowire Transistor (GeNWT) depending on variable channel length (Lg). It also studies the possibility of using them as a temperature nanosensor. The MuGFET simulation tool was exploited to investigate the characteristics of the considered nanowire transistors. Current-voltage characteristics with different values of temperature with channel length [Lg = 25, 45, 65, 85 and 105 nanometer (nm)], were simulated. MOS diode mode connection suggested measuring the temperature sensitivity of SiNWT and GeNWT too. Three (3) electrical characteristics namely; (i) Subthreshold Swing (SS), (ii) Threshold voltage (VT), and (iii) Drain-induced barrier lowering (DIBL) were evaluated and compared for both NWTs. The obtained results show that SiNWT achieved a better temperature sensitivity with channel length range between 25 nm to 105 nm at operation voltage (VDD) range 1 V to 5 V nm. It is very clear that the temperature sensitivity increased remarkably by increasing channel length for both of SiNWT and GeNWT as well, but in SiNWT the sensitivity is more steady compared to GeNWT that showing less sensitivity. Moreover, SiNWT shows better result in terms of electrical performance metrics for various channel length at T = 300 K comparing with GeNWT.

Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4.

Characterization of silicon nanowire transistor

This paper analyses the temperature sensitivity of Silicon Nanowire Transistor (SiNWT) depends on the diameter (D.ch) of channel. In addition, it also investigates the possibility of utilizing SiNWT as a Nano- temperature sensor. The MuGFET simulation tool has been utilized to conduct a comprehensive simulation to evaluate both electrical and temperature characteristics of SiNWT. Current-voltage characteristics with different values of temperature and with a varying diameter of the Nano wire channel (D.ch = 80, 40, 20 and 10 nm), were simulated. Diode operating mode connection of the transistor is suggested for measuring the temperature sensitivity of SiNWT. As simulation results demonstrated, the best temperature sensitivity was occurred at lower temperature with increasing the channel diameter. We also illustrate the impact of varying temperature and channel diameter on electrical characteristics of SiNWT including, Subthreshold Swing (SS), Threshold voltage (V.th), and Drain-induced barrier lowering (DIBL), which were proportionally increased with the operating temperature.

Electrical Сharacterization of Ge-FinFET Transistor Based on Nanoscale Channel Dimensions

Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors' dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate and a successor to conventional planar devices in nanoscale technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest of researchers in both academia and industry. However, aggressively scaling down of channel dimensions, will degrade the overall performance due to detrimental short channel effects. In this paper, we investigate the impact of downscaling of nano-channel dimensions of Germanium Fin Feld Effect Transistor (Ge-FinFET) on electrical characteristics of the transistor, namely; ION/IOFF ratio, Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to conduct a simulation study to achieve optimal channel dimensions by considering channel length (L), width (W), and oxide thickness (TOX) individually. In addition, the effects of simultaneous consideration of all dimensions by exploiting a scaling factor, K was evaluated. According to the obtained simulation results, the best performance of Ge-FinFET was achieved at a minimal scaling factor, K = 0.25 with 5 nm channel length, 2.5 nm width, and 0.625 nm oxide thickness.

Temperature Characteristics of Silicon Nanowire Transistor Depending on Oxide Thickness

Among various sensing and monitoring techniques, sensors based on field effect transistors (FETs) have attracted considerable attention from both industry and academia. Owing to their unique characteristics such as small size, light weight, low cost, flexibility, fast response, stability, and ability for further downscaling, silicon nanowire field effect transistor (SiNW-FET) can serve as an ideal nanosensor. It is the most likely successor to FET-based nanoscale devices. However, as the dimensions (channel length and diameter) of SiNWT channel are shrinking down, electrical and temperature characteristics of SiNWTs should be affected, thereby degrading transistor performance. Although applications of SiNWTs as biological and/or chemical sensors have been extensively explored in the literature, less attention has been devoted to utilize such transistors as temperature sensors. Therefore, this paper characterizes the temperature sensitivity of SiNWT depending on the channel oxide thickness and also presents the possibility of using it as a nano-temperature sensor. The MuGFET simulation tool was used to investigate temperature characteristics of the nanowire. Current-voltage characteristics with different values of temperature and with different thickness of the nanowire gate (oxide thickness (TOX) = 1, 2, 3, 4, and 5 nm), were simulated. Metaloxide- semiconductor (MOS) diode mode connection was suggested for measuring the temperature sensitivity of SiNWT. Several operating voltages (0.25 to 5 V) with various working temperature (250 to 450 K) were investigated. The obtained results show that the highest temperature sensitivity was achieved by increasing oxide thickness to 5 nm. The impact of the considered temperature on SiNWT characteristics demonstrates the possibility of utilizing it as a temperature nanosensor.

Nano-Dimensional Properties of Si-FinFET Transistor Based on ION/IOFF Ratio and Subthreshold Swing (SS)

This paper presents design the optimal channel dimensions for Silicon Fin Feld Effect Transistor (Si-FinFET) for improvement electrical characteristic of Si-FinFET depending on the electrical characteristics of the channel (I ON /I OFF , SS, VT, DIBL). The MuGFET simulation tool has been using to investigate the electrical characteristics of Si-FinFET. The current voltage characteristics has been simulating with different dimensions channel (length, width and oxide thickness). The best channel dimensions of Si-FinFET observed based on electrical characteristics at the working voltage VDD range of 0-5 V. Note that the results with the scaling channel dimensions. Depending on I ON /I OFF ratio higher value, and nearest SS to the ideal SS, the best scaling channel dimensions (K) will be K=0.25 at VDD=5 V and K=0.25 at VDD=0.5 V.

Investigation of FinFET as a Temperature Nano-Sensor Based on Channel Semiconductor Type

This paper represents the temperature effect on FinFET transistor and the possibility of using it as a temperature nano-sensor. The MuGFET simulation tool was used to investigate temperature characteristics of the FinFET. Current-voltage characteristics with different values of temperature were simulated. MOS diode connection suggested using the FinFET transistor as a temperature nano-sensor. The final results shows that the best FinFET used as a nano- sensor is with GaAs because it has the greatest ΔΙ (=10.9%) referring to ΔΙ at 25°C, and the best FinFET stable with increasing working temperature is Si-FinFET because it has the lowest ΔΙ (=6%) referring to ΔΙ at 25°C.

Dimensional Effect on DIBL in Silicon Nanowire Transistors

Drain-induced barrier lowering (DIBL) is crucial in many applications of silicon nanowire transistors. This paper determined the effect of the dimensions of nanowires on DIBL. The MuGFET simulation tool was used to investigate the characteristics of the transistors. The transfer characteristics of transistors with different dimensions were simulated. The results show that longer nanowires with smaller diameters and lower oxide thickness decrease DIBL and tend to possess the best transistor characteristics.

Nanowire Dimensions Effect on ON/OFF Current Ratio and Sub-Threshold Slope in Silicon Nanowire Transistors

This paper shows the effect of the dimensions of nanowires on threshold voltage, ON/OFF current ratio, and sub-threshold slope. These parameters are critical factors of the characteristics of silicon nanowire transistors. The MuGFET simulation tool was used to investigate the characteristics of a transistor. Current-voltage characteristics with different dimensions were simulated. Results show that long nanowires with low diameter and oxide thickness tend to have the best transistor characteristics.