MSB Bits Research Articles

VADF: V ersatile A pproximate D ata F ormats for Energy-Efficient Computing

Approximate computing (AC) techniques provide overall performance gains in terms of power and energy savings at the cost of minor loss in application accuracy. For this reason, AC has emerged as a viable method for efficiently supporting several compute-intensive applications, e.g., machine learning, deep learning, and image processing, that can tolerate bounded errors in computations. However, most prior techniques do not consider the possibility of soft errors or malicious bit-flips in AC systems. These errors may interact with approximation-introduced errors in unforeseen ways, leading to disastrous consequences, such as the failure of computing systems. A recent research effort, FTApprox (DATE’21) proposes an error-resilient approximate data format. FTApprox stores two blocks, starting from the one containing the most significant valid (MSV) bit. It also stores location of the MSV block and protects them using error-correcting bits (ECBs). However, FTApprox has crucial limitations such as lack of flexibility, redundantly storing zeros in the MSV, etc. In this paper, we propose a novel storage format named Versatile Approximate Data Format (VADF) for storing approximate integer numbers while providing resilience to soft errors. VADF prescribes rules for storing, for example, a 32-bit number in either 8-bit, 12-bit or 16-bit numbers. VADF identifies the MSV bit and stores a certain number of bits following the MSV bit. It also stores the location of the MSV bit and protects it by ECBs. VADF does not explicitly store the MSB bit itself and this prevents VADF from accruing significant errors. VADF incurs lower error than both truncation methodologies and FTApprox. We further evaluate five image-processing and machine-learning applications and confirm that VADF provides higher application quality than FTApprox in the presence and absence of soft errors. Finally, VADF allows the use of narrow arithmetic units. For example, instead of using a 32-bit multiplier/adder, one can first use VADF (or FTApprox) to compress the data and then use a 8-bit multiplier/adder. Through this approach, VADF facilitates 95.97% and 79.3% energy savings in multiplication and addition, respectively. However, the subsequent re-conversion of the 8-bit output data to 32-bit data using Inv-VADF(16,3,32) diminishes the energy savings by 9.6% for addition and 0.56% for multiplication operation, respectively. The code is available at https://github.com/CandleLabAI/VADF-ApproximateDataFormat-TECS .

Proposed approximate hybrid memory architecture for handheld multimedia devices

Nowadays Handheld multimedia devices demand is growing rapidly, as the demand for mobility in work and lifestyle increases. Power consumption has become the paramount concern in the design of Handheld multimedia battery-operated devices. Approximate computing promises energy efficiency computing paradigms when small quality degradation is permissible. Most multimedia processing is image or video processing, where the end user is a human. The imperceptibility of the human visual system is to allow the output of this processing to be approximate rather than accurate. This research paper proposed an energy-efficient Moving Picture Experts Group 4 (MPEG-4) video decoder architecture with a circuit-level approximate method for Handhandle multimedia devices. Hence, in this research work instead of using conventional 6T memory cells during video decoding processing, an approximate Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSBs) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSBs) are stored in the conventional 6T bit cells for more optimal configurations compared with previous work. The failure probability of 6T cells is significantly large 0.0988 at 600 mV supply voltage (as compared to 0.28*10^-2 at 800 mV supply voltage), leading to a decrease in the output quality of the decoded video. The hybrid memory matrix formulation calculates that storing higher-order MSB bits in highly stable memory cells will provide high-quality video processing compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. The proposed approximate 6T/8T hybrid memory units, and evaluate them to demonstrate the efficacy of our approach. Simulations result indicate power savings of up to 50% with an insignificant loss in output quality (3.6 dB) when compared to the conventional memory unit. Compared to the hybrid and conventional 6T memory array at 600 mV supply voltage, the worst minimum PSNR is 15.04 dB improved.

MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply

The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.

VLSI Implementation of a High Speed Multiplier Using on the Fly Conversion Technique

An On the Fly Conversion Technique included array multiplier with optimum design. A multiplier loaded with N-Bit results to produce 2N bit partial products. The discermentation of bits will be as (2N) -(N/2) in addition with N/2 Bits. The Engineering of the bits differed with each other depending on the positions in their structure. This paper is considered in implementing an array multiplier put in effect using On the Fly Conversion Technique staked with Hybrid Full Adders abates the time delay. Instead of using a truncation or addition approach, the array multiplier described in this paper is constructed and implemented using a standard array multiplier scheme. The OTFC Logic Is used to boost Carry-Propagation at the final stage of Multiplication.To incorporate the MSB bits in parallel with the LSB bits, all of the final carry outputs were added into the OFTC circuit to get the result in less time. This work leads to achieve the sustainable development goals in the industry, innovation and Infrastructure.

A 12-bit, 1.1-GS/s, Low-Power Flash ADC

In this article, an efficient architecture for a low-power, high-resolution flash analog-to-digital converter (flash ADC) is presented. It operates at 12-bit resolution with a sampling frequency of 1.1 GS/s. The architecture is a segmented one consisting of three subflash ADCs that we call SADC1, SADC2, and SADC3. During the operation, SADC1 detects the MSB bit, and SADC2 detects the intermediate bits, while SADC3 detects the finer bits of the flash ADC. Furthermore, SADC1 has a 1-bit resolution, SADC2 has a 6-bit resolution, and SADC3 has a 5-bit resolution. The binary operation related to 12-bit resolution is achieved by combining the subflash ADCs, thermometer digital outputs, and an encoder. The ADC has been fabricated in Global Foundry (GF) 65-nm standard CMOS process. The measured performance parameters show a differential nonlinearity (DNL) of ±0.24 LSB, an integral nonlinearity (INL) of ±0.45 LSB, a signal-to-noise and distortion ratio (SNDR) of 64.55 dB, a spurious-free dynamic range (SFDR) of 73.9 dB, and an effective number of bits (ENOB) of 10.43 bits. Also, power consumption is found to be 15.10 mW at 1.1-GS/s sampling frequency and 1.2-V supply voltage. The ADC achieves an FOM of 9.95 fJ/conversion-step (c-s) at the Nyquist input frequency and occupies a core area of 0.084 mm².

A novel DICOM image encryption with JSMP map

Recent times have seen a massive rise in the transmission and storage of DICOM images. This work proposes a cryptosystem with the sturdy JSMP map, for the pixel data of the DICOM file. The proposed system is designed to work in the bit plane level for high resilience. To achieve an effective cryptosystem, the number of bit planes generated depends on the bits stored attribute and not on the conventional method of bits allocated of each pixel. Only the MSB bit planes that contribute more to the details of the image are shuffled with the JSMP chaotic keys. Then the shuffled image is reconstructed by combining all the MSB and LSB bit planes. Finally, a robust cipher image is generated by diffusing the reconstructed image with a random image generated with JSMP map. The novelty and uniqueness of the system lie in its capability of encrypting DICOM images with any pixel depth. The distinctive feature of this system is the unique key generation algorithm and the variable number of keys, which contributes to high sensitivity and entropy. Performance measures of the encrypted image illustrate the robustness of the cryptosystem in the health information system.

Reversible data hiding in encrypted images with block-based adaptive MSB encoding

Contemporary cloud storage and social media networks have matured and; as a result, the privacy protection of image content in these applications have attracted more attention. Reversible data hiding in encrypted images (RDHEI) is an efficient technique to embed additional data such as timestamps, watermarks, and copyright information into encrypted images to protect the image content. This paper proposes a reversible data hiding scheme in encrypted images based on a block-based adaptive MSB encoding technique (BAME-RDHEI). The content owner first uses a block-based image encryption method, including block permutation, pixel permutation in each block, and the block-based bitwise exclusive-or operation, to encrypt an image. This specific image encryption method preserves the relevance of the MSB bit planes in each block, and the block-based adaptive MSB encoding technique can be applied to classify and encode eight block types according to the number of MSB bit planes where all the values are all ‘1’ or ‘0’. After embedding the indicators that are generated by Huffman coding into the first MSB bit plane of each block, the remaining values of these MSB bit planes can be vacated for data embedding. The receiver can extract additional data, decrypted the image or recover the original image according to the different keys. The experimental results demonstrate that our proposed scheme provides enhanced security, significantly improves the embedding rate, and obtains higher visual quality for the decrypted image compared to other state-of-the-art schemes.

Energy efficient switching scheme based on MSB-split structure for SAR ADC

An energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSB-split and merge-and-split techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76% switching energy reduction comparing to the conventional solution. Furthermore, without requiring for a third reference voltage makes it especially suitable for ADC design under low supply voltage. Additionally, LSB-down technique is employed, which reduces the total capacitor DAC area by 50%. The simulated differential-nonlinearity and integrated-nonlinearity are 0.27 and 0.21LSB, respectively, demonstrating that the proposed switching algorithm has a relatively good linearity.

CMOS integrated delay chain for X-Ku band applications

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 $$\upmu \hbox {m}$$ CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of $$1.2\times 2.7$$ mm$$^{2}$$ and has no DC power consumption.

Improvement of Gray ROM-Based Encoder for Flash ADCs

In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-[Formula: see text] thermometer codes to 2-of-[Formula: see text] codes ([Formula: see text]). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-[Formula: see text] codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-[Formula: see text] codes are turned to [Formula: see text] gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, [Formula: see text] MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-[Formula: see text]m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30[Formula: see text]ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50[Formula: see text]mW and 13.90[Formula: see text]mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.

High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure

Dynamic performance of the current-steering digital-to-analog converter (DAC) is mainly affected by the mismatch-induced nonlinearity. Dynamic-element-matching (DEM) method has been widely employed to effectively improve the amplitude and timing mismatches. However, the maximum performance improvement is constrained by the conventional separate-segment structure for the current source array. In this brief, a DEM DAC with nested-segment structure is proposed to improve the mismatch performance. Compared with the best spurious-free dynamic range (SFDR) values obtained by the conventional DEM DACs, Monte Carlo simulations demonstrate that the proposed DAC achieves higher performance improvement with the same MSB bit width. The largest improvement occurs at MSB bit width of 3 with the 6.95- and 4.68-dB gain over two conventional designs, respectively. In terms of the digital complexity, the proposed architecture employs at least $2.7\times$ fewer multiplexers compared with the reported DEM DACs, while achieving comparable dynamic performance. Fabricated in 130-nm CMOS process, the proposed 12-bit 100-MS/s DAC occupies 0.21 mm2. Measurement results show that $1.9\times$ integral nonlinearity reduction ratio and 15.5-dB SFDR improvement from 46.6 to 62.1 dB at near Nyquist frequency are achieved.

Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD Audio Amplifiers

The paper presents an original architecture and implementation of 9-bit LBDD hybrid DPWM circuit for Class-BD digital audio amplifier. The input PCM signals are directly transformed into 24-bit LBDD DPWM signals and then are requanized to the 9-bit digital outputs using noise-shaping process to support high fidelity with practical values of time resolution, and finally are converted by the DTCs into the two physical trains of 1-bit PWM signals. The architecture of the proposed Class-BD hybrid DPWM circuit is composed of two Class-AD ones. The hybrid quantizer converts 6 MSB bits using counter method, based on the STM32F407xx microcontroller, while the remaining 3 LSB bits - using a method based on the Programmable Tapped Delay Line (PTDL). All necessary time waveforms are generated on the base of the internal microcontroller oscillator 168 MHz. The proposed 9-bit Class-DB DPWM circuit allows to attain SNR of 110 dB and THD about 0,2% within the audio baseband, at switching frequency of 328.1 kHz, clock frequency of 42 MHz and modulation index M = 0.95. Basic verification of algorithm and circuit operation as well as simulation and preliminary experimental results have been performed.

Linear in dB, sub 0.2 dB gain-step CMOS programmable gain amplifier for ultrasound applications

In this paper a new approach for controlling the gain of a programmable gain amplifier (PGA) using an eight-bit digital word has been proposed. Eight stages of R–2R ladder attenuators have been employed for attenuating the input signal. The output of the ladder network feeds the nine gm stages as a part of the PGA. Making use of three MSB bits of the control word, at each instance just the two successive gm stages are active whose tail currents are precisely determined to set the PGA linear gain in dB. A current bank composed of 32 current sources has been used for driving the tail currents of the active gm stages. The current sources that bias the active gm stages are controlled by the five LSB bits of the digital control word. Thanks to the proposed technique, the values of the current sources are determined so that the gain of the circuit is based on a ratio-metric parameter making the circuit less sensitive to process variations. For verification of the proposed idea, a differential PGA is design in a 0.18 µm 1.8 V CMOS technology. The gain of the designed circuit changes from 20.8 to −27.4 dB in 256 steps linearly in dB so that the maximum gain error respect to its ideal value is less than 0.03 dB in different corner cases. At the maximum gain, the bandwidth and the input referred noise voltage of the PGA are 150 MHz and 3.5 nv/√Hz, respectively, while the overall circuit draws 6 mA from a 1.8 V power supply.

Self-embedding fragile watermarking based on reference-data interleaving and adaptive selection of embedding mode

In this paper, we propose a novel self-embedding fragile image watermarking scheme for tampering recovery based on reference-data interleaving mechanism and adaptive selection of embedding mode. During watermark embedding, reference bits are derived from the interleaved, scrambled MSB bits of original image, and then are combined with authentication bits to form the watermark bits for LSB embedding. Different with the reported schemes with the fixed embedding mode, the proposed scheme not only has two types of embedding modes, i.e., overlapping-free embedding and overlapping embedding, but also utilizes the adaptively flexible numbers of MSB and LSB layers to achieve satisfactory performances for different tampering rates. Also, detailed analyses are given to provide the theoretical values of watermarked-image quality, perfect recovery probability, and recovered-image quality, which are used to conclude the optimal choice of embedding modes. Experimental results show the effectiveness and superiority of the proposed scheme compared with some state-of-the-arts schemes.

Fully Reused VLSI Architecture of FM0/Manchester Encoding Technique for Memory Application

In this paper a fully reused VLSI architecture of FM0/Manchester encoding technique for memory application has been proposed. In this paper we are encoding the 1 bit data into 16 bit data and storing it into a memory of certain address location given by the linear feedback shift register (LFSR),whose input is taken from the pseudo random sequence generator (PRSG). The encoded 16 bit data is stored into memory controller; the encoded data is decoded back into 1 bit data under the condition: when MSB bit is at logic state 1. By using FM0/Manchester encoding and decoding technique, the data will be secure, this process is easy and faster to carry out. This paper develops a fully reused VLSI architecture, and also exhibits an efficient performance.