MOSFET Width Research Articles

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m/I_D</i> -based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layout-dependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c_db</i> ) and source-to-bulk ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c_sb</i> ) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.

Calibration and Implementation of Heat Cycle Requirement of MQ-7 Semiconductor Sensor for Detection of Carbon Monoxide Concentrations

Carbon monoxide (CO) is a prevalent and widely distributed air pollutant. Its detection and control in residential and industrial environments are essential in order to avoid potentially severe health consequences in people. The aim of this study was to conduct an air quality assessment by measuring CO concentrations using the MQ-7 Semiconductor Sensor. The MQ-7 sensor is a commonly accessible and cost-effective sensor with specific heating needs. The objectives of the study are to provide a method for implementing heater cycle requirements, equipment-less calibration, and the derivation of a formula for measuring CO concentrations in parts per million (ppm). A procedure for calibrating gas sensors is discussed, which involves measuring the sensing resistance and calculating the resistance ratio. The resistance ratio is then used to calculate the target gas concentration in ppm using a formula derived with the aid of Microsoft Excel, such that it represents the original CO characteristic curve provided in the sensor datasheet with greater accuracy. An N-channel MOSFET and Pulse Width Modulated (PWM) voltage were used to get the required heater voltage levels. The methodology developed for calibrating and deriving the equation to determine the target gas concentration can be used for any MQ semiconductor sensor and does not require any special equipment.

Design of sub-threshold current memory circuit for low power ADC

In this paper, it is proposed that the current memory circuit should be operated in sub-threshold region for low power of Analog to Digital Converter (ADC).When to store the sampling information of the analog signal and to pass to the next stage is used with the current memory circuit. The current memory circuit is used when the sampling information of the analog signal is to be transmitted, after it is stored. The supply voltage of designed circuit is supplied by 1.2V for the operation of sub-threshold region. Regarding the transistor in the simulation, it is used by the BSIM3 model of 0.35μm process in TSMC. According to the design conditions for minimizing effect at Clock-Feedthrough, it was designed with switch MOSFET width of 1μm, dummy MOSFET width of 8.82μm and memory MOSFET width of 2μm. From the simulation result, it was demonstrated that memory time in current memory circuit was 0.5ms at operations of sub-threshold. Power consumption of designed sub-threshold current memory circuit is 11.17μW.

Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.

A derivative method to determine a MOSFET's effective channel length and width electrically

A new method is presented to determine the channel-width reduction ΔW and the channel-length reduction ΔL in CMOS transistors. By measuring the transconductance of certain sets of n-channel and p-channel MOSFET's biased at low gate and drain voltages in the linear region, a set of derived first-order linear equations is used iteratively to solve for ΔW and ΔL. The results agree with the process observations of fabricated CMOS devices.

Gate electrode RC delay effects in VLSI's

A poly-silicon gate electrode can be considered as a distributed RC line. The delay induced by this RC time constant can become a limitation in designing high-speed VLSI's. This effect, called the gate electrode RC delay effect (GERDE), is studied for short-channel MOSFET's. A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a simple lumped-circuit model is also described. The future trends of the GERDE are investigated and it is concluded that the GERDE gets more severe for shorter channel MOSFET's, but, if the gate width is confined up to 30 µm, the GERDE can be neglected for MOSFET's with a channel length of more than 0.8 µm. For a large conductance, division of the MOSFET width is shown to be effective through experiments.

Gate Electrode RC Delay Effects in VLSI's

A poly-silicon gate electrode can be considered as a distributed RC line. The delay induced by this RC time constant can become a limitation in designing high-speed VLSI's. This effect, called the gate electrode RC delay effect (GERDE), is studied for short-channel MOSFET's. A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a simple lumped-circuit model is also described. The future trends of the GERDE are investigated and it is concluded that the GERDE gets more severe for shorter channel MOSFET's, but, if the gate width is confined up to 30/spl mu/m, the GERDE can be neglected for MOSFET's with a channel length of more than 0.8 /spl mu/m. For a large conductance, division of the MOSFET width is shown to be effective through experiments.