Abstract
A new method is presented to determine the channel-width reduction ΔW and the channel-length reduction ΔL in CMOS transistors. By measuring the transconductance of certain sets of n-channel and p-channel MOSFET's biased at low gate and drain voltages in the linear region, a set of derived first-order linear equations is used iteratively to solve for ΔW and ΔL. The results agree with the process observations of fabricated CMOS devices.
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