Abstract
A unified and computationally efficient SPICE model for accurate prediction of the I-V characteristics of small-geometry lightly doped drain (LDD) MOSFETs is described. It is based on the enhancement of the SPICE LEVEL3 MOS model and a novel parameter extraction method. It supports the design of both short-channel and narrow-gate-width LDD MOSFETs with any kind of channel or field implant. A semiempirical approach to the modeling of the threshold voltage of LDD MOSFETs, in which the small-geometry effect is implemented, is demonstrated. The model is applicable to LDD MOSFETs with effective channel lengths and channel widths down to the submicrometer range and nonuniformity doped substrate. An LDD device is considered to be an intrinsic MOSFET in series with two external resistors. These two resistors account for the drain-to-source series resistance effect and are functions of drain-source voltage in the linear device-operating region. In addition, automatic extraction of device parameters for SPICE built-in LDD MOSFET models has been developed. Comparisons between the measured and modeled threshold voltages and I-V characteristics show excellent agreement for a wide range of channel lengths, widths and biases. >
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