MOSFET Circuits Research Articles

NBTI Mechanism Based on Hole-Injection for Accurate Lifetime Prediction

The evaluation method of Negative Bias Temperature Instability (NBTI) based on hole-injection is proposed for accurate lifetime prediction of MOS devices. The acceleration parameters are most important for accurate lifetime prediction. Proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but the injected hole injection quantity to the gate insulator film. The degradation mechanism in the excessive voltage and excessive temperature stresses are different from that in the operation conditions. In the relatively high hole-injection stress, the mechanism is also different from that in the operation conditions. It is considered that the difference is caused by the excess enhancement of the hole energy in the inversion layer. In the relatively low hole-injection stress, the degradation mechanism becomes the same as that in the operation conditions. The accurate lifetime prediction in MOSFET level and circuit level can be realized by hole-injection acceleration method.

Efficient De-Embedding Technique for 110-GHz Deep-Channel-MOSFET Characterization

In this letter, a de-embedding procedure is proposed to accurately extract the small signal equivalent circuit of advanced MOSFETs up to 110GHz. This efficient procedure is easy to implement using only one open dummy structure to de-embed the external parasitics (probe pads, interconnecting transmission line, and top-down metallic interconnections and via holes) and is in particular suitable for industrial online automatic test. The method has been validated in the case of 65-nm n-MOSFETs and is proved to be efficient up to 110GHz

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability

An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform

A Resonant Gate-Drive Circuit Capable of High-Frequency and High-Efficiency Operation

This paper deals with a new resonant gate-drive circuit for power MOSFETs. The proposed gate-drive circuit is characterized by a resonant inductor connected in series to the gate terminal of the MOSFET. It is possible to charge or discharge the input capacitance of the MOSFET by using the resonance between the inductor and the input capacitance. Experimental results are shown to verify the viability of the resonant gate-drive circuit. As a result, the proposed resonant gate-drive circuit reduces its power consumption to one tenth, compared with a conventional one. It was experimentally clarified that the proposed circuit makes it possible to improve efficiency of a high-frequency inverter using MOSFETs.

Growth Kinetics and Electrical Properties of Ultrathin Silicon Dioxide Layers

In this paper, the growth kinetics and electrical properties of ultrathin silicon-dioxide layers are reviewed. Topics discussed here include the onset of oxide growth, the effects of temperature, substrate orientation, dopant type and concentration, and stress on oxide growth kinetics. The use of in situ real-time ellipsometry to control the rapid- thermal oxidation of silicon will be presented. The electrical properties of the ultrathin silicon-dioxide layers will be discussed, especially the contact potential difference in MOS devices and its dependence on the processing history and substrate orientation which will be explained in terms of the role of partial-charge-transfer dipoles at the oxide/silicon interface. Finally, gate tunneling considerations in MOSFET design, modeling, characterization, and circuit performance will be briefly presented.

Low Cost Gate Drive Circuit for MOSFETs and IGBTs

This work presents the design and implementation of a general purpose low cost drive circuit for insulated gate electronic power devices such as MOSFET and IGBT. The proposed drive circuit implementation is explained in detail and the results and waveforms obtained when the drive circuit is used in a chopper circuit with IGBT are presented.

Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells

An ‘atomistic’ circuit simulation methodology is developed to investigate intrinsic parameter fluctuations introduced by discreteness of charge and matter in decananometer scale MOSFET circuits. Based on the ‘real’ doping profile, the impact of random device doping on 6-T SRAM static noise margins are discussed in detail for 35 nm physical gate length devices. We conclude that SRAM may not gain all the benefits of future bulk CMOS scaling, and new device architectures are needed to scale SRAM down to future technology node.

Equivalent Saturated MOSFET Circuit with Wide Input Range

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS - VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

Performance of Solid-State High-Voltage Pulsers for Biological Applications—A Preliminary Study

Modern semiconductor devices, such as power MOSFETs, are becoming increasingly viable as candidates for high-speed switching of high-voltage/high-current pulse circuits that are required for applications in biotechnology, such as bulk sterilization and in medical applications, such as electroporation. A survey of literature on electroporation shows that exponential and square (also known as rectangular) pulses varying in magnitudes from millivolts to kilovolts with millisecond to nanosecond pulse widths have been successfully used by researchers. High voltages and currents are reliably controlled by these devices when implemented in typical circuits. However, conventional MOSFETs in substrate-mounted standard packages are not designed to accommodate the extreme requirements that pulsed power applications demand. It is necessary to test these devices for their performance in a range of pulsed power applications and study their characteristics. This paper presents the simulation of modern semiconductors in pulsed power circuits. These tests characterize the limits of a device's performance when driven to nanosecond rise and fall times and nanosecond to microsecond pulse widths. MOSFET circuits reported in the literature were used for this purpose. Two of these circuits were also built and tested in our laboratory. In general, simulation results compared well with experimental results.

Visual dead-reckoning for motion control of a Mecanum-wheeled mobile robot

Given an omni-directional mobile platform using four Mecanum wheels requires further a capability to be programmed to achieve various motion behaviours and intelligence. This paper describes an undergraduate solution to the problem involving both hardware and software developments. With a path following behaviour as the aim, the research focused predominantly upon; sensors for dead-reckoning, motor drive, closed-loop feedback control, and microcontroller interfacing and programming. A four channel high power MOSFET and relay H-Bridge driver circuit board was designed for driving four motors. Two optical mice were attached to the front and rear of the robot giving positional feedback for closed-loop control and dead-reckoning for navigation. A Mitsubishi M16C/62 microcontroller was interfaced to these TTL compatible devices and subsequently programmed to implement various robotic behaviours. A closed-loop control scheme using three independent PID controllers was implemented to follow three degrees-of-freedom motions, i.e., x- and y-movement and rotation motions. The path following performance of the robot was tested in both open-loop and closed-loop modes and the optical mice were found to be a promising but inexpensive sensor, providing dead-reckoning for robot motion control.

Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study

Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted ( near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain ( V ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si:H photodiode

In this paper we first present the integration of amorphous silicon photodiodes with a fully depleted silicon on isolator (FD SOI) MOSFET circuit. Taking the advantage of the better subthreshold characteristic of FD SOI MOSFETs with respect to bulk devices, a very simple SOI circuit integrated with the amorphous silicon photodiode is presented to significantly improve the ratio of the circuit output current when the diode is illuminated to when it is not. The use of one additional reference source voltage to adjust the operating point of the photodiode, allows to obtain a very significant increase in this current ratio, much higher than what can be obtained using a simple diode. Circuit solutions used to amplify the diode current under illumination are usually more complicated and involve a capacitor or more transistors than the circuit we present. All the other properties of the photodetector, as its spectral characteristic and linear dependence of detection with light intensity are maintained. The circuit can also be used in conjunction with other circuits for further amplification and/or processing.

Resistive equivalents in CMOS

A novel single transistor MOSFET circuit equivalent for a resistor is presented. The resistor value is tunable over six orders of magnitude. By exploring short channel effects a linear range of more than 2.5 V with <1% relative error is verified by simulation.

Design of a multiple‐operand redundant binary adder

AbstractThis paper describes a novel multiple‐operand redundant binary adder. The novel multiple‐operand addition algorithm can eliminate the carry propagation chain by dividing the input operands into an even place part and an odd place part, and adding them. The multiple‐operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary tree‐structured method. A hardware model for the proposed adder implemented by the bidirectional current‐mode MOSFET circuit technology is described. Simulations have been made with HSPICE in order to verify the function of the proposed circuit. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(10): 1–9, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10182

Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data

A practical and efficient approach for estimating the MOSFET device and circuit performance distributions is presented. The proposed method is based on the Latin hypercube sampling technique and direct extracting and utilizing the statistical information obtained from a population of parametric test data. Using this approach, a set of worst-case models taking into account data correlations and equal probability constraints is developed. The procedure allows for a systematical and accurate way to predict the performance spread and worst case of MOSFET circuits, as well as a greatly reduced computation time for statistical simulation. Measured data of two digital circuits are included in support of the modeling work.

Exploiting electrothermal oscillations for identifying MOSFET thermal parameters

Electrothermal oscillations in electronic circuits are in general regarded as parasitic dynamic phenomena. This paper shows how these phenomena may be exploited to identify the value of thermal resistance and capacitance of the RC network modelling heat diffusion. Measurement of the period of oscillations and bifurcation analysis of the stability of the equilibrium point are two approaches that may possibly lead to a reasonable estimate of these parameters. In this paper, we present both methods applied to two specific MOSFET circuits. In particular, the oscillation period of a current-mirror circuit and bifurcation analysis of a simple one-MOSFET circuit are analysed in detail. For the bifurcation analysis approach, theory and experimental results are successfully compared to simulation in order to validate the proposed model.

Analysis of 1/f noise in switched MOSFET circuits

Analysis of 1/f noise in MOSFET circuits is typically performed in the frequency domain using the standard stationary 1/f noise model. Recent experimental results, however, have shown that the estimates using this model can be quite inaccurate especially for switched circuits. In the case of a periodically switched transistor, measured 1/f noise power spectral density (psd) was shown to be significantly lower than the estimate using the standard 1/f noise model. For a ring oscillator, measured 1/f-induced phase noise psd was shown to be significantly lower than the estimate using the standard 1/f noise model. For a source follower reset circuit, measured 1/f noise power was also shown to be lower than the estimate using the standard 1/f model. In analyzing noise in the follower reset circuit using frequency-domain analysis, a low cutoff frequency that is inversely proportional to the circuit on-time is assumed. The choice of this low cutoff frequency is quite arbitrary and can cause significant inaccuracy in estimating noise power. Moreover, during reset, the circuit is not in steady state, and thus frequency-domain analysis does not apply. This paper proposes a nonstationary extension of the standard 1/f noise model, which allows us to analyze 1/f noise in switched MOSFET circuits more accurately. Using our model, we analyze noise for the three aforementioned switched circuit examples and obtain results that are consistent with the reported measurements.

Determining non-quasi-static small-signal equivalent circuit of a RF silicon MOSFET

We present an accurate non-quasi-static small-signal MOSFET model incorporating distributed channel and substrate resistances to extend the frequency limit of the model validity to higher frequencies. The model parameters are accurately determined using a new semi-analytical extraction technique combining analytical and optimization approaches as an effective way to attain a global minimum. The validity of the model and parameter extraction method is justified by observing excellent agreements between the measured and modeled S-parameters in the wide range of frequency.

On the topology and number of operating points of MOSFET circuits

This paper reviews previous theory regarding the existence and uniqueness of dc operating points possessed by bipolar transistor circuits and applies it to MOSFET circuits. Two primary results are presented. First, it is shown that certain previous topological results regarding the uniqueness of dc operating points for bipolar junction transistor and JFET circuits do not strictly hold for MOSFET circuits. Second, a two-transistor MOSFET circuit that possesses five operating points is presented. This circuit is contrasted with previous results that indicate that two-transistor BJT circuits can possess no more than three operating points. The existence of this MOSFET circuit is justified by showing how the previous result breaks down in the case of circuits containing MOSFETs.