MoS2 FETs Research Articles

The effect of the stacking arrangement on the device behavior of bilayer MoS2 FETs

The effect of the stacking arrangement on the device behavior of bilayer MoS2 FETs

Comprehensive investigation on CF4/O2-plasma treating the interfaces of stacked gate dielectric in MoS2 transistors

CF4/O2-plasma is used to treat the interfaces of gate stacks (MoS2/Al2O3/ ZrO2/p+-Si), and its effects on the electrical performance of the few-layered MoS2 transistors have been investigated. Experimental results show that excellent electrical properties have been achieved for the MoS2 transistors with CF4/O2-plasma treated stacked gate dielectric, especially for the F-treated ZrO2 device: high mobility of 53.7 cm2/Vs, small subthreshold swing of 117 mV/dec and high on/off ratio of 2.7 × 107. The involved main mechanisms lie in the facts that: (i) the MoS2/dielectric interface is improved through the F- passivation on the oxygen vacancies in the dielectric, decreasing the dangling bonds and surface roughness of the dielectric; (ii) the dielectric constant (k) of the gate stack dielectric is increased because of suppressed growth of low-k Zr-silicate interlayer and improved dielectric quality by forming ZrF and AlF bonds; (iii) CF4/O2-plasma treatment on the ZrO2 surface can result in F incorporation in both ZrO2 and Al2O3, thus giving the best passivation effects on oxygen vacancies and oxide traps near/at the MoS2/dielectric interface. These results indicate that CF4/O2-plasma treatment is an effective way for improving the bulk and interface qualities of gate dielectrics and thus the electrical properties of MoS2 FETs.

Reliable and highly sensitive biosensor from suspended MoS2 atomic layer on nano-gap electrodes

The uneven morphology and the trapped charges at the surface of the traditionally used supporting substrate-based 2D biosensors produces a scattering effect, which leads to a irregular signals from individually fabricated devices. Though suspended 2D channel material has the potential to overcome scattering effects from the substrates but achieving reliability and selectivity, have been limiting the using of this biosensor technology. Here, we have demonstrated nanogap electrodes fabrication by using the self-assembly technique, which provides suspension to the 2D-MoS2. These nano-spacing electrodes not only give suspension but also provide robustness strength to the atomic layer, which remains freestanding after coating of the Hafnium oxide (HfO2) as well as linkers and antibodies. For evaluating the electrical characteristics of suspended MoS2 FET, gating potential was applied through an electrolyte on the suspended MoS2 transistor. This helped in achieved a lower subthreshold swing 70 mV/dec and ON/OFF ratio 107. Later, pH detection was conducted at room temperature, which showed an impressive sensitivity of ~880 by changing 1 unit of pH. We have also successfully shown Escherichia coli (E. coli) bacteria sensing from the suspended MoS2 transistor by functionalizing dielectric layer with E. coli antibodies. The reported biosensor has shown the ~9% of conductance changes with a lower concentration of E. coli (10 CFU/mL; colony-forming unit per mL) as well as maintain the constant sensitivity in three fabricated devices. The obtained enhancement in the sensitivity of devices and its effect on biomolecules detection can be extened to other biomolecules and this type of architecture has the potential to detect COVID-19 viruses based biomolecules.

Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS2 FETs for SoC Scaling

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices.

Improved Electrical Properties of Top-Gate MoS2Transistor With NH3-Plasma Treated HfO2as Gate Dielectric

The effects of NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric on electrical characteristics of top-gate (TG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs are investigated. The experimental results show that the increase of off-state current after growing HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top-gate dielectric can be considerably decreased by NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , because the N incorporation from the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treatment can effectively eliminate the oxygen vacancies and reduce the positive oxide charges in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The fabricated TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs with the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric achieve excellent electrical performances: high on-off ratio of 2.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , high carrier mobility of 78~87 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and near-ideal subthreshold swing of 72mV/dec. Therefore, the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric is highly beneficial for fabricating high-performance TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs.

Enhanced mobility of MoS2 field-effect transistors by combining defect passivation with dielectric-screening effect* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774064, 61974048, and 61851406).

A facile method of combining the defect engineering with the dielectric-screening effect is proposed to improve the electrical performance of MoS2 transistors. It is found that the carrier mobility of the transistor after the sulfur treatment on the MoS2 channel is greatly enhanced due to the reduction of the sulfur vacancies during vulcanization of MoS2. Furthermore, as compared to those transistors with HfO2 and SiO2 as the gate dielectric, the Al2O3-gate dielectric MoS2 FET shows a better electrical performance after the sulfur treatment, with a lowered subthreshold swing of 179.4 mV/dec, an increased on/off ratio of 2.11×106, and an enhanced carrier mobility of 64.74 cm2/V⋅s (about twice increase relative to the non-treated MoS2 transistor with SiO2 as the gate dielectric). These are mainly attributed to the fact that a suitable k-value gate dielectric can produce a dominant dielectric-screening effect overwhelming the phonon scattering, increasing the carrier mobility, while a larger k-value gate dielectric will enhance the phonon scattering to counteract the dielectric-screening effect, reducing the carrier mobility.

An Atomically Thin Optoelectronic Machine Vision Processor

2D semiconductors, especially transition metal dichalcogenide (TMD) monolayers, are extensively studied for electronic and optoelectronic applications. Beyond intensive studies on single transistors and photodetectors, the recent advent of large-area synthesis of these atomically thin layers has paved the way for 2D integrated circuits, such as digital logic circuits and image sensors, achieving an integration level of ≈100 devices thus far. Here, a decisive advance in 2D integrated circuits is reported, where the device integration scale is increased by tenfold and the functional complexity of 2D electronics is propelled to an unprecedented level. Concretely, an analog optoelectronic processor inspired by biological vision is developed, where 32 × 32 = 1024 MoS2 photosensitive field-effect transistors manifesting persistent photoconductivity (PPC) effects are arranged in a crossbar array. This optoelectronic processor with PPC memory mimics two core functions of human vision: it captures and stores an optical image into electrical data, like the eye and optic nerve chain, and then recognizes this electrical form of the captured image, like the brain, by executing analog in-memory neural net computing. In the highlight demonstration, the MoS2 FET crossbar array optically images 1000 handwritten digits and electrically recognizes these imaged data with 94% accuracy.

Rapid Four-Point Sweeping Method to Investigate Hysteresis of MoS2 FET

Hysteresis is a frequently observed phenomenon in the transfer characteristics of thin film transistors. Charge trapping/de-trapping processes of gate oxide and gate-channel interface are commonly known to be the origin of hysteresis and correlated to low frequency noise (LFN) properties of the devices. In this letter, a rapid four-point sweeping method (RFSM) is proposed to reveal the dependence of hysteresis, as well as the distribution of effective trap density on sweeping rate and gate bias range. Based on the RFSM, the hysteresis properties of four-layer MoS2 FETs are studied in detail. The experimental results demonstrate that the hysteresis and trap density at different frequencies and gate voltages, which could further roughly map the traps with different time constants and energy depths, can be obtained by the simple RFSM. Trap density estimated by RFSM shows a comparable range with that extracted from LFN, indicating that the traps inducing the hysteresis may also cause LFN.

(Invited) Multi-Level Non-Volatile Memory in Au/Monolayer MoS2/Au Structures

The wide range of electronic and optical properties exhibited by two dimensional semiconductors, and their variation physical thickness, opens up new possibilities to create ultra-short length transistors [1], steep-slope switches [2, 3], light detecting/emitting devices [4, 5] and chemical/physical sensors. Recently, it was demonstrated that monolayer 2D semiconductors can also display resistive switching [6]. In this work we demonstrate that a single layer of large area CVD-grown moly disulphide (MoS2) sandwiched between two metal electrodes can be tuned to exhibit multi-level non-volatile resistive memory, with resistance values separated by 5 orders of magnitude. The switching process is unipolar and thermochemically driven (TCM memory) requiring significant Joule heating in the RESET process. Temperature dependent electrical measurements will be presented which demonstrate the charge transport mechanism varies between the initial state (IS), the high resistive state (HRS) and low resistive state (LRS). The temperature dependent behavior of the SET, RESET process is consistent with the creation and passivation of sulfur vacancies in the MoS2 monolayer. Conductive AFM measurements confirm that the multi-filamentary resistive memory effects are inherent to a single crystalline MoS2 triangle and not necessarily dependent of grain boundaries. This work demonstrates that potential for 2 terminal, multi-state, resistive memories for next generation digital memory and neuromorphic applications.[1] S. B. Desai et al., "MoS2 transistors with 1-nanometer gate lengths," Science, vol. 354, no. 6308, pp. 99-102, 2016.[2] S. Bhattacharjee, K. L. Ganapathi, S. Mohan, and N. Bhat, "A sub-thermionic MoS2 FET with tunable transport," Applied Physics Letters, vol. 111, no. 16, p. 163501, 2017.[3] D. Sarkar et al., "A subthermionic tunnel field-effect transistor with an atomically thin channel," Nature, vol. 526, no. 7571, p. 91, 2015.[4] K. Roy et al., "Graphene–MoS 2 hybrid structures for multifunctional photoresponsive memory devices," Nature nanotechnology, vol. 8, no. 11, p. 826, 2013.[5] X. Zhou et al., "2D Layered Material‐Based van der Waals Heterostructures for Optoelectronics," Advanced Functional Materials, vol. 28, no. 14, p. 1706587, 2018.[6] R. Ge et al., "Atomristor: Nonvolatile Resistance Switching in Atomic Sheets of Transition Metal Dichalcogenides," Nano letters, vol. 18, no. 1, pp. 434-441, 2017.

Strain-Dependent Polar Optical Phonon Scattering and Drive Current Optimization in Nanoscale Monolayer MoS2 FETs

Recently, microelectromechanical system has been used to dynamically strain atomically thin materials including MoS2. While strain can significantly modulate the electronic and phonon structures of monolayer MoS2, its impact on electron transport, especially in the dissipative regime, has not been well explored. In this paper, using a three-dimensional particle-based quantum-corrected Monte Carlo device simulator, the effects of uniaxial and biaxial strain on room-temperature electron transport in a model monolayer molybdenum disulphide (MoS2) based field-effect transistor have been investigated. In the beginning, the simulator has been validated against recently published experimental results. Overall, strain in monolayer MoS2 strongly affects the polar optical phonon modes as well as the electronic bandstructure. Uniaxial strain breaks the degeneracy of E′ Raman mode and results in phonon softening. In this case, our results show that, for both E+ and E− Raman modes, ON current first increases for up to 3.7% of applied strain and then decreases as the strain is increased further. As for biaxial strain, we consider the effects of both tensile and compressive stresses. We find that the application of biaxial tensile strain boosts the ON current for up to 4% of strain. Especially, biaxial tensile strain leads to ~ 15.56% increase in the ON current, which is highest for any type of applied stress.

Self-heating Characteristics of Mo Electrodes and MoS2 FET Using IR Thermal Imaging Microscope

In this study, the static and transient thermal characteristics of molybdenum electrodes induced by self-heating process are reported. The corresponding local temperatures of the electrodes were measured using an infrared thermal imaging microscope system. Maximum temperature is observed to increase (80 {260 °C depending on the width of the electrode) at the narrow region of the electrodes. In addition, the measured temperature was linearly proportional to the applied power per unit width. The transient thermal measurement performed in the range between 10 Hz and 100 kHz has shown that the temperature fluctuation begins to decrease at 1 kHz and saturate to a certain level. In addition, the self-heating effect on an atomically-thin two-dimensional molybdenum disulfide field-effect transistor operating in ambient conditions was also observed.

Air stable and reversible n-type surface functionalization of MoS2 monolayer using Arg and Lys amino acids

Schematic and transfer properties of a MoS2 FET decorated with Arg or Lys amino acid, thus showing effective electron doping with air stability.

Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations

Device operations of the monolayer molybdenum disulfide (MoS2) based FETs are analyzed using first principle atomistic simulations, revealing the similarity of device operation in monolayer and Si transistors. Taylor expansion is employed on Si potential modeling framework, assuming an ultra-thin (delta function like) channel for MoS2 devices. The method accurately reproduces the gate control of the MoS2 FETs in both long channel and short channel transistors including the subthreshold characteristics. First principle simulations verify the developed model, suggesting that the monolayer MoS2 MOSFET can be modeled by extending Si MOSFET equations with incorporating material parameters.

(Invited) Investigation of Interfacial Charge Transfer Doping of 2D MoS2

Layered two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) have attracted a great deal of attention because of their exciting electrical and optical properties and their potential applications in electronic and optoelectronic devices. Because of ultra low volume and chemically inert surface of 2D materials, it is challenging to achieve controlled doping of 2D materials. Recently, interfacial charge transfer induced doping of 2D materials have gained significant attention. In this talk, I will present electrical transport studies of 2D molybdenum disulfide (MoS2) field effect transistors decorated with zero dimensional (0D) gold (Au) nanoislands. I will discuss how the Au nanoisland coverage affects the interfacial charge transfer based doping and tailor the electrical properties of the host material. From the detailed low temperature electron transport measurements, I will elucidate the role of 2D-0D interface on the transport properties of MoS2 FETs.

Total-Ionizing-Dose Response of MoS2Transistors With ZrO2and h-BN Gate Dielectrics

The total-ionizing-dose response of few layer MoS2 transistors with ZrO2 or h-BN gate dielectrics is investigated under various bias conditions. Defects in MoS2 and surrounding dielectric layers significantly affect radiation-induced trapping. For devices with ZrO2 dielectrics, much larger negative Vth shifts and peak transconductance degradation are observed for irradiation under negative and ground bias than under positive bias. The h-BN devices exhibit positive threshold voltage shifts under negative-bias irradiation. For both ZrO2 and h-BN passivated devices, the peak transconductance degradation results from charge trapping at the surface of the MoS2 or in nearby oxides. Changes in defect energy distributions of MoS2 FETs during X-ray irradiation are characterized via temperature-dependent low-frequency noise measurements. Density functional theory calculations are performed to provide insight into the pertinent defects.

Reliability of scalable MoS2 FETs with 2 nm crystalline CaF2 insulators

Two-dimensional (2D) semiconductors are currently considered a very promising alternative to Si for channel applications in next-generation field-effect transistors of sub-5 nm designs. However, their huge potential cannot be fully exploited owing to a lack of competitive insulators which are required to effectively separate the channel from the gate, while being scalable down to few nanometers thicknesses. Recently we have made an attempt at addressing this issue by using crystalline CaF2 insulators and demonstrated competitive MoS2 devices with the insulator thickness of only about 2 nm. Here we report a detailed study of the performance, reliability and thermal stability of these devices. We demonstrate that, in contrast to SiO2 and other amorphous oxides, CaF2 has a very low density of insulator defects which are responsible for the hysteresis and long-term drifts of the transistor characteristics. At the same time, CaF2 exhibits smaller leakage currents and higher electric stability compared to hBN. By comparing our MoS2 transistors with CaF2 fabricated using MoS2 films of different quality, we show that the major limitations on the performance and reliability of these devices come from the bare channel rather than from the superior CaF2 insulator. Finally, we perform the first study of degradation mechanisms only observed for tunnel-thin gate insulators in 2D devices. While these degradation mechanisms are similar for hBN and CaF2, they are less pronounced in CaF2. Our results therefore present a solution to a very important roadblock on the way towards fully scalable 2D nanoelectronics with competitive performance and reliability.

Bias Temperature Stress Instability of Multilayered MoS2 Field-Effect Transistors With CYTOP Passivation

Bias temperature stress instability on multilayered MoS2 FETs was systematically investigated with the device scheme encapsulated with amorphous fluoropolymers [cyclized transparent optical polymer (CYTOP)] for the secure of minimization of external gas ambient effects. Large threshold voltage shifts ( $\Delta {V}_{\textsf {th}}$ ) for the negative bias temperature stress (NBTS) were observed, compared to the positive bias temperature stress (PBTS). Herein, the asymmetry behaviors on $\Delta {V}_{\textsf {th}}$ , observed in this paper, are ascribed to the sulfur vacancy in MoS2 layers, leading to large hole traps compared to electron traps in MoS2 layers. Moreover, high-temperature-sensitivity [ ${d}$ ( $\Delta {V}_{\textsf {th}}$ )/ dT ] on $\Delta {V}_{\textsf {th}}$ for PBTS than NBTS was observed, and their origins are possibly due to synergetic effects associated with large trap energy distribution ( ${k}_{o}{T}$ ) for electron trap levels.

Polarization induced switching in PZT back gated multilayer MoS2 FETs for low power non-volatile memory

We demonstrated polarization induced switching in lead zirconium titanate (PZT) back gated multilayer MoS2 ferroelectric field effect transistors (Fe-FETs) for low power non-volatile memory devices. In this work, we investigate the influence of the interface between ferroelectric and 2D (MoS2) materials on the transistor characteristics for non-volatile memory applications. We fabricated Fe-FET devices with multilayer MoS2 as a channel material and polycrystalline and single crystal PZT thin films as the ferroelectric gate materials. The Fe-FET with polycrystalline PZT as a gate shows good memory characteristics; however, the hysteresis in transfer characteristics of the Fe-FET is in the clockwise direction (anti-hysteresis), which indicates that the transistor characteristics are not purely controlled by the ferroelectric charge. On the other hand, the Fe-FET devices with a single crystal PZT as the gate shows stable memory characteristics with a clear anti-clockwise hysteresis, which shows that the transistor characteristics are purely controlled by the ferroelectric charge. To understand the source of the anti-hysteresis and the interface between the ferroelectric and 2D materials, we have performed polarization switching at nanoscale using piezo force microscopy (PFM). The local piezoelectric hysteresis loop measured by PFM reveal that the polarization reversal in polycrystalline MoS2/PZT heterostructures is due to inhomogeneous polarization distribution, oxygen vacancies and high surface roughness of the polycrystalline PZT thin films. Our MoS2 Fe-FET devices with epitaxial PZT as a gate exhibit low switching voltages ≤2 V (much lower than the reported 2D-FET devices (8–20 V)), high ON-OFF ratios ≥104 (comparable to state of the art Fe-FET devices) and reproducible hysteresis behaviour with good sustainability over 200 cycles of switching operations. This study helps with the understanding of the fundamental phenomenon for anti-hysteresis, and the realization of low power and reliable non-volatile memory devices.

Improved interfacial and electrical properties of few-layered MoS2 FETs with plasma-treated Al2O3 as gate dielectric

ALD Al2O3 films treated respectively by N2, O2 and NH3 plasmas are used as gate dielectrics to fabricate few-layered MoS2 FETs. As compared with the control sample without any plasma treatment, the devices with different plasmas treatments achieve better electrical properties, with the NH3-treated device having the best results: highest carrier mobility of 39.3 cm2/Vs (~1.65 times higher than that of the control sample), smallest subthreshold swing of 90.9 mV/dec, largest on/off ratio of 1.5 × 107 and negligible hysteresis. These are attributed to the fact that the NH3 plasma treatment can (1) effectively passivate the oxygen vacancies in Al2O3 and decrease the dangling bonds at the Al2O3 surface, thus reducing the traps at/near the Al2O3/MoS2 interface; (2) increase the k value of the dielectric by N incorporation to enhance the screening effect on the Coulomb impurity scattering. In addition, these plasma treatments can adjust the MoS2 FET from depletion mode to enhancement mode by introducing negative ions into the gate dielectric.

Transitions between channel and contact regimes of low-frequency noise in many-layer MoS2 field effect transistors

Low-frequency noise studies in transition metal dichalcogenides have considered the layer-thickness dependence but generally do not separate channel contributions from those of contact/access regions. Here, we study the voltage-dependent 1/f noise and the resistance correlation in MoS2 FETs with an ∼142 atomic layer-thickness channel and three different lengths. The gate-voltage dependence of noise can be separated into a channel contribution, with a comparable Hooge parameter for the three devices and a contact/access region contribution. Separation of these contributions allows the evaluation of the channel noise mechanism and can be used to explain the length-dependence of the transition region between contact- and channel-dominated regimes.