MOS HEMTs Research Articles

Optimizing Bio-Sensor Design With Support Vector Regression Technique for AlGaN/GaN MOS–HEMT

Optimizing Bio-Sensor Design With Support Vector Regression Technique for AlGaN/GaN MOS–HEMT

Dual gate AlGaN/GaN MOS-HEMT biosensor for electrical detection of biomolecules-analytical model

This paper proposes an analytical model for a dual gate AlGaN/GaN Metal oxide semiconductor-high-electron-mobility transistor (MOS-HEMT) biosensor for electrical detection of neutral species such as Biotin, Keratin, ChOx, and Zein. When only one subband is occupied and the AlGaN layer is assumed to have been fully ionized, the Fermi–Dirac statistic and 2D state density are used to produce a self-consistent calculation of the carrier density in the quantum well at the interface. It is done by analyzing the impact of biomolecule concentration by inserting a biomolecule of appropriate dielectric permittivity in the cavity area beneath the gate region. The impact of cavity length has been analyzed on the sensor’s performance. The proposed device significantly changes the channel potential, transconductance, drain current, and threshold voltage. Dual gate structures offer superior resistance to short channel effects. Due to enhanced transport characteristics, high carrier mobility, drain current, and a variety of other factors, double gate MOS HEMT outperforms single-gate MOS HEMT. The maximal transconductance, drain on sensitivity, and the maximal drain current that has been attained in this work is 0.017 s, 0.22 and 0.129 mA, respectively, for biomolecule concentration, N b = 3 × 1012. Among all the biomolecules used in this study, Keratin has achieved the maximum shift in threshold voltage and transconductance of 0.4 V and 0.016 s. The increase in current for Keratin, Biotin, Zein, and ChOx is 0.67%, 78%, 17%, and 42%, respectively, from single to dual gate AlGaN/GaN MOS-HEMT. SiO2, Al2O3, and HfO2 oxides have been compared by filling them in the left side of the cavity. Dual gate AlGaN/GaN MOS-HEMT biosensor presents an opportunity to develop robust, low-cost, specific detection and analysis of neutral biomolecule. The analytical model provides good results for drain current according to the comparison of simulation and analytical model findings.

Performance evaluation of electrical properties of GaN MOS-HEMTs based biosensors for rapid detection of viruses

In this work AlGaN/AlN/GaN MOS-HEMTs based biosensors have been proposed and simulated for the rapid test and ultrasensitive detection of various viruses. The proposed device employs two-dimensional (2D) III-nitride semiconductor materials for the biosensing detection. A cavity has been created in the oxide of the proposed GaN MOS HEMTs to detect biomolecules and viruses. An analytical model of GaN MOS-HEMTs has been modulated by dielectric constant of the virus, thus providing insight into the device physics. A 2D calibrated simulation of the proposed bioelectronic device has been performed and the results have been compared with an analytical model developed. Various analyses have been performed in this work including the sensitivity analysis. The simulations have revealed that the high dielectric constant of the virus reflects high sensitivity of the proposed GaN MOS-HEMTs based biosensors. Further, the studies show that the proposed structure can be used for the detection of different viruses in future, especially those which are harmful to human life.

Double Gate Double-Channel AlGaN/GaN MOS HEMT and its Applications to LNA with Sub-1 dB Noise Figure

Double Gate Double-Channel AlGaN/GaN MOS HEMT and its Applications to LNA with Sub-1 dB Noise Figure

Performance Investigation of Power Inverter Components Submersed in Subcooled Liquid Nitrogen for Electric Aircraft

Investigating the performance of power electronics devices and thus power inverters at cryogenic temperatures for electric aircraft systems are of great interest. Accordingly, the purpose of this study is to examine the inverter circuit technologies used in cryogenically-cooled electric aircraft applications from three perspectives: inverter topologies, power capabilities, and electromagnetic interference (EMI) that may occur. At a cryogenic temperature, the characteristics of five power semiconductor switches with different technologies (Si MOS, SiC MOS, and GaN HEMT) used in cryogenically-cooled electric aircraft inverters were tested and the results were presented. Furthermore, the low-temperature performance of three types of capacitors commonly used in power electronics inverters was investigated. The research findings provide crucial considerations for the research and development of power inverters cooled by sub-cooled liquid nitrogen for modern electric aircraft.

A Novel Bidirectional AlGaN/GaN ESD Protection Diode.

Despite the superior working properties, GaN-based HEMTs and systems are still confronted with the threat of a transient ESD event, especially for the vulnerable gate structure of the p-GaN or MOS HEMTs. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of a GaN power system. In this study, an AlGaN/GaN ESD protection diode with bidirectional clamp capability was proposed and investigated. Through the combination of two floating gate electrodes and two pF-grade capacitors connected in parallel between anode or cathode electrodes and the adjacent floating gate electrodes (CGA (CGC)), the proposed diode could be triggered by a required voltage and possesses a high secondary breakdown current (IS) in both forward and reverse transient ESD events. Based on the experimental verification, it was found that the bidirectional triggering voltages (Vtrig) and IS of the proposed diode were strongly related to CGA (CGC). With CGA (CGC) increasing from 5 pF to 25 pF, Vtrig and IS decreased from ~18 V to ~7 V and from ~7 A to ~3 A, respectively. The diode’s high performance demonstrated a good reference for the ESD design of a GaN power system.

Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C

In this work, the DC behavior of AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MO(I)SHEMTs) with two different gate dielectrics (Al2O3 and Si3N4) is analyzed through the experimental comparison of their basic and analog parameters. The transistors with Si3N4 insulator are more closely related to the normally-off devices (less negative threshold voltage) and less affected by the short channel effects (better DIBL behavior). Although the devices with Si3N4 layer presented a double conduction, that results in anomalous transconductance behavior, it is more suitable for analog applications since the Al2O3 devices suffer large self-heating. The very high gate leakage of Si3N4 MISHEMT degrades the subthreshold regime, which decreases the transistor efficiency at weak inversion. On the other hand, the devices with Si3N4 insulator present relatively large Early voltage and consequently high intrinsic voltage gain in strong inversion, reaching 84 V/V (38.5 dB). Even at high temperatures the intrinsic voltage gain is practically the same, degrading only 1.5 dB from 25 °C to 150 °C for a long channel device.

Investigation of interfaces and threshold voltage instabilities in normally-off MOS-gated InGaN/AlGaN/GaN HEMTs

Polarization engineering is a promising approach to achieve high positive threshold voltage (Vth) in GaN-based metal-oxide-semiconductor high electron mobility transistors (MOS HEMTs). In this paper, we investigate all critical interfaces of polarization-engineered normally-off Al2O3/InGaN/AlGaN/GaN MOS HEMTs using transmission electron microscopy and X-ray photoelectron spectroscopy. Mechanisms of threshold voltage (VTH) instabilities are also analyzed. Devices were subjected to positive-bias stress-recovery experiments to capture the transient change in Vth. We propose a model that explains observed peculiar behavior and discuss the role of 2-dimensional hole gas (2DHG) in Al2O3/InGaN/AlGaN/GaN MOS HEMTs Vth shift.

Threshold voltage control of non-recessed GaN MOS HEMTs and recessed GaN MOS FETs by AlxGa1−xN back barrier

Threshold voltage (Vth) control of a GaN MOS transistor by AlxGa1−xN back barrier was systematically studied. Non-recessed GaN MOS HEMTs and recessed GaN MOS FETs with an AlxGa1−xN (x = 0%, 3%, 5%, 8%) back barrier layer were fabricated on the same 6 inch GaN-on-Si wafers and characterized. Al2O3 gate-insulator thickness was changed from 20 to 100 nm to evaluate the Al2O3/GaN interface fixed charge. The Vth of the GaN MOS transistor increases with increasing in Al content x of the AlxGa1−xN back barrier layer and decreasing in Al2O3 thickness. The dependences of Vth on Al content x and Al2O3 thickness were different between non-recessed and recessed transistor. The different dependences of Vth on Al content x and Al2O3 thickness were explained well by the newly introduced surface donor model, which compensate not only the surface polarization charge but also the surface electric field.

Single Pulse Charge Pumping Measurements on GaN MOS-HEMTs: Fast and Reliable Extraction of Interface Traps Density

In this article, we report on the single pulse charge pumping (SPCP) measurements as a method to extract the interface trap density ( ${N} _{\text {it}}$ ) on the GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS–HEMTs). The electron capture and emission processes are monitored in the time domain and studied during the rising and falling edges of a gate voltage pulse. Two different gate stacks are studied by SPCP including epitaxial Mg0.25 Ca0.75O (MgCaO) and amorphous Al2O3. The signature charge pumping (CP) current peaks are observed enabling a direct extraction of ${N} _{\text {it}}$ as low as $1.4\times 10^{{11}}$ cm−2 with gate voltage sweeping from OFF-state to ON-state in the GaN MOS-HEMT with epitaxial MgCaO gate stack. A significant reduction of ${N} _{\text {it}}$ by the MgCaO gate stack compared to Al2O3 only gate stack is also confirmed by the SPCP method. SPCP realizes a direct ${N} _{\text {it}}$ measurement on GaN transistors and confirms the high quality interface between the single crystalline epitaxial MgCaO and GaN. It is verified as a fast and reliable interface characterization method on III–V HEMTs, gate-all-around nanowire transistors, and 2-D transistors, which do not exhibit body contacts as the conventional Si transistors needed for conventional CP measurements.

Epitaxial Lift-Off Technology for Large Size III–V-on-Insulator Substrate

III-V materials can be a very good channel candidate for monolithic 3D (M3D) integration due to the potential of high-performance and lower process temperature as compared with Si, since a low process temperature is crucial to avoid degradation of bottom devices. For III-V M3D integration, material transfer techniques are important, and such processes should be enabled by low process costs on a large wafer scale. In this study, we propose an InGaAs channel transfer technique by wafer bonding, epitaxial lift-off and III-V layers grown on Si substrate. Effective mobility of fabricated MOS HEMTs using transferred InGaAs layer was 1.3 times higher than that of Si MOSFETs. The proposing channel transfer technique would be useful for M3D integration because it provides wafer scalability, cost-effectiveness, back-gate biasing, and etc.

Low-Voltage Circuit Breakers Based on WBG Solid-State Devices

Conventional circuit breakers suffer from two main deficiencies: they are slow to operate and develop an electrical arc. These may be overcome by using solid-state switches which in turn introduce other problems, most significantly power dissipated while in the on-state. Nevertheless, a number of solid-state devices are candidates for implementation as low-voltage circuit breakers and there are several options based on the semiconductor material that may function as high-power switches. This paper presents a unique, extensive and systematic evaluation of these options. Voltage-controlled devices are selected due to the simplicity of the controlling circuit and their resilience to [Formula: see text]/[Formula: see text]-induced switching. Properties of fully solid-state circuit breakers are established and systematic comparisons are made among switches built of silicon and other wide bandgap (WBG) devices such as SiC MOS and GaN HEMT transistors. Using SPICE simulation it is shown that solid-state circuit breakers (SSCBs) based on WBG devices exhibit superior characteristics compared with silicon devices, with faster switching and higher voltage and current ratings. Hybrid circuit breakers, combining both conventional and solid-state switches, are discussed too and a new design circuit is simulated and compared to both conventional and fully solid-state designs.

Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and −3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (∼0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device, while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (∼0.14 eV above EF) and trapping at the oxide/GaN cap interface states.

Electrical transportation and piezotronic-effect modulation in AlGaN/GaN MOS HEMTs and unpassivated HEMTs

The metal-oxide-semiconductor high-electron-mobility transistors (MOS HEMTs) have been demonstrated and compared with the conventional unpassivated AlGaN/GaN HEMTs. 20nm SiO2 layer deposited by PECVD (plasma enhanced chemical vapor deposition) is used as a gate-insulator in the SiO2/AlGaN/GaN MOS HEMT. We present empirical evidence that MOS HEMTs outperforms the conventional HEMTs with DC performance. The piezotronic effect is then introduced to modulate the drain current of HEMTs by applying external stresses on the devices. The saturated drain currents of the HEMT devices decrease under in-plane tensile strain which is resulted from the piezoelectric polarization effect at the AlGaN/GaN interface. Working mechanism of the piezotronic effect modulating properties of 2DEG (two dimensional electron gases) and electrical transportation behavior of the HEMT devices are conducted via the band energy profile in the AlGaN/GaN heterstructure. 3D strain model is also induced to simulate and illustrate the proposed working mechanism further. This study provides in-depth comprehension into working principle of the piezotronic effect modulating physical properties of 2DEG in AlGaN/GaN hetero structures as well as guidance for the potential application in HEMT and MEMS/NEMS devices.

Self‐aligned normally‐off metal–oxide–semiconductor n++GaN/InAlN/GaN high electron mobility transistors

Self‐aligned normally‐off n++GaN/InAlN/AlN/GaN MOS HEMTs with a recessed gate show scalable threshold voltage between 1.3 to 3.7 V, which increases with the gate oxide thickness. Al2O3 or HfO2 gate insulators were grown by ALD at 100 °C so that one photoresist mask could be used for the gate recessing, ALD and metal lift‐off. A low density of the barrier surface donors ∼1 × 1013 cm−2 stems from the low thermal budged during the HEMT processing and explains the threshold voltage behaviour. Maximal IDS reaches ∼0.4 A/mm despite 2‐μm gate length and 8‐μm source‐to‐gate distance invariant to the threshold voltage. It is shown that for the present device Al2O3 provides better gate insulation than HfO2, however, the latter may be more appropriate for highly scaled short gate‐length HEMTs. Schematic picture of the self‐aligned InAlN/GaN MOS HEMT.

Ni/Au–Al2O3 gate stack prepared by low-temperature ALD and lift-off for MOS HEMTs

We present the technology and performance of AlGaN/GaN MOS HEMTs with Al2O3 gate insulation. Definition of the Ni/Au gate metallization and underlying Al2O3 into a gate stack was realized by a single photolithographic step and lifted-off. 10nm thick Al2O3 layers were deposited by the low-temperature (100°C) atomic layer deposition (ALD), using ALD processes with (PA) and without (T) remote plasma enhancement. A dielectric constant of as deposited Al2O3 εr∼7.5 was determined from C–V measurements. The MOS HEMTs properties were evaluated from I–V, and C–V measurements, and the PA and T modes for the ALD deposition of Al2O3 in the gate stacks were compared also after consecutive annealing/passivation steps.

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

In this study, the rare earth erbium oxide (Er2O3) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (Nt) of the MOS–HEMT were 125mV/decade and 4.3×1012cm−2, respectively. The dielectric constant of the Er2O3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166V for the conventional HEMT to –196V for the Er2O3 MOS–HEMT.

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al 2O 3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al 2O 3 gate insulation and surface passivation. About 12 nm thin high- κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al 2O 3 growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ∼0.6 A/mm ( V GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al 2O 3 dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.

Development and characteristic analysis of a field-plated Al2O3/AlInN/GaN MOS—HEMT

We present an AlInN/AlN/GaN MOS—HEMT with a 3 nm ultra-thin atomic layer deposition (ALD) Al2O3 dielectric layer and a 0.3 μm field-plate (FP)-MOS—HEMT. Compared with a conventional AlInN/AlN/GaN HEMT (HEMT) with the same dimensions, a FP-MOS—HEMT with a 0.6 μm gate length exhibits an improved maximum drain current of 1141 mA/mm, an improved peak extrinsic transconductance of 325 mS/mm and effective suppression of gate leakage in both the reverse direction (by about one order of magnitude) and the forward direction (by more than two orders of magnitude). Moreover, the peak extrinsic transconductance of the FP-MOS—HEMT is slightly larger than that of the HEMT, indicating an exciting improvement of transconductance performance. The sharp transition from depletion to accumulation in the capacitance—voltage (C—V) curve of the FP-MOS—HEMT demonstrates a high-quality interface of Al2O3/AlInN. In addition, a large off-state breakdown voltage of 133 V, a high field-plate efficiency of 170 V/μm and a negligible double-pulse current collapse is achieved in the FP-MOS—HEMT. This is attributed to the adoption of an ultra-thin Al2O3 gate dielectric and also of a field-plate on the dielectric of an appropriate thickness. The results show a great potential application of the ultra-thin ALD-Al2O3 FP-MOS—HEMT to deliver high currents and power densities in high power microwave technologies.

Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs

The effect of interface states on the current–voltage characteristics in the sub-threshold region of three different types of III–V based transistor architectures has been studied using a drift–diffusion based numerical simulator. Experimentally extracted interface state density profile is included in the simulation to analyze their effect on the sub-threshold response of InGaAs based MOSFETs, MOS HEMTs and tunnel FETs. Based on the Fermi-level position at the oxide/semiconductor interface and the corresponding interface state density ( D it), the sub-threshold response for the three devices can vary, with tunnel FETs having the least sub-threshold degradation due to D it.