MOS Current Mode Logic Circuits Research Articles

Design of Linear Feedback Shift Register for Low Power Applications

This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing

Power dissipation and delay product have emerged to be crucial issue, which prove to decrease the performance of microprocessor. The MOS current mode logic (MCML) is an evolving logic family that is attracting interest owing to its high speed operation, reliable performance in comparison to the CMOS logic family. However, the MCML suffers from constant static power dissipation, which, if left unmanaged, would result in an inordinate energy requirement in large scale ICs. In order to resolve this challenge, the newly introduced system designed a modified MOS current mode logic (modified MCML) that has remarkable characteristics of lesser power dissipation, better switching frequency and greater processing speed. With the aim of achieving low power dissipation, the dynamic MOS current mode logic (dynamic MCML) is proposed. Dynamic MCML circuits integrate the benefits of MCML circuits with those that of the dynamic logic families for achieving great performance using a low-supply voltage along with low-power dissipation. The results obtained from simulation show that the newly introduced design model of dynamic MCML yields greater power conservation and higher processing speed in comparison with conventional CMOS technology, MCML and modified MCML with regard to power dissipation and power delay product.

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (t p ), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10– $100 \times $ smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the $C$ -slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10– $40\times $ lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting $1.6\times $ lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits

In this paper, we realize a high performance arithmetic circuits which is faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for arithmetic circuits. This new dynamic logic family is known as Dynamic Current Mode Logic (DyCML). DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. A major advantage of the DyCML is the dynamic current source, which achieves smaller delays compared to the basic MCML circuits. Other advantages inherited from MCML are high performance and robustness to supply voltage scaling. DyCML gates reduce power dissipation by reducing the output voltage swing. We compare a set of arithmetic circuits implemented in Dynamic Current Mode Logic with the other dynamic logic styles. Simulation and test results show that DyCML circuits are superior to DDCVS logic styles in terms of power dissipation. A 2-bit multiplier, full adder & xor/xnor gate in DyCML style is fabricated in 180nm CMOS technology. 2-bit multiplier and a full adder dissipate 145.1 µW and 55.14 µW respectively at 40 MHz for a voltage swing of 1.2V in DyCML style.

Near-threshold Computing and Performance Optimization of MOS Current Mode Logic Circuits

Near-threshold Computing and Performance Optimization of MOS Current Mode Logic Circuits

Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

A Power-Gating Scheme for MOS Current Mode Logic Circuits

MOS Current-Mode Logic (MCML) is widely used for high-speed circuits. However, the MCML circuits have large static power consumptions due to their constant operation currents. This paper presents a power-gating scheme for MCML circuits to reduce their static power dissipations in sleep mode. The PMOS transistors for linear load resistors of MCML circuits are used for power-gating switches. A power-gating control circuit consisting of NMOS and PMOS transistors is added for switching power-gating switches under the control of the sleep signal. The structure and operation of the proposed power-gating scheme are presented. In order to verify the correctness of the proposed power-gating scheme, several basic cells and a full-adder based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130nm technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.2877

Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits

Scaling supply voltage is an efficient technique to achieve low power-delay product. This study presents low-power Single-Rail MOS Current Mode Logic (SRMCML) circuits which operate on near-threshold region. The near-threshold operations for the basic SRMCML circuits such as inverter/buffer, OR2/NOR2 and 2/NAND2, OR3/NOR3 and XOR3/NXOR3 are investigated. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process by varying supply voltage from 0.6V to 1.3V with 0.1V steps. Based on the simulation results, lowering supply voltage is advantageous. The power dissipations of the proposed near-threshold SRMCML basic gates are almost the same as the conventional Dual-Rail MCML (DRMCML) circuits and the delay of the SRMCML is less than the DRMCML because of its single-rail scheme.

Near-Threshold Computing of High Speed MOS Current Mode Logic Circuits

Near-Threshold Computing of High Speed MOS Current Mode Logic Circuits

Single-Rail MOS Current Mode Logic Circuits for Low-Power and High-Speed Applications

Abstract MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dualrail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic single-rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process. The power dissipations of the basic SRMCML cells are compared with the conventional dual-rail MCML ones. The power dissipation of the proposed SDMCML circuits is almost the same as the conventional dual-rail ones. The SRMCML circuit can attain smaller powerdelay product than dual-rail MCML ones because of its single-rail scheme.

A Methodology for the Design of MOS Current-Mode Logic Circuits

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8 × 8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8 × 8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35 μm standard CMOS process.

MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.

Design and optimization of MOS current mode logic for parameter variations

An automated optimization-based design strategy is proposed for MOS current mode logic (MCML) circuits to overcome the complexities of the design procedure. The proposed design methodology determines the values of the design variables that achieve minimum power dissipation while attaining the required performance. Furthermore, comprehensive analytical formulations of the design parameters associated with MCML circuits are presented to provide guidelines for MCML designers. The proposed design methodology has the advantages of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on MCML operation is presented. The proposed strategy is used to design two popular circuits in a 0.18μm CMOS technology, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the circuit parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as technology scales down is investigated to highlight the importance of designing for variability in future CMOS technologies.

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.