Abstract
Scaling supply voltage is an efficient technique to achieve low power-delay product. This study presents low-power Single-Rail MOS Current Mode Logic (SRMCML) circuits which operate on near-threshold region. The near-threshold operations for the basic SRMCML circuits such as inverter/buffer, OR2/NOR2 and 2/NAND2, OR3/NOR3 and XOR3/NXOR3 are investigated. All circuits are simulated with HSPICE at the SMIC 130 nm CMOS process by varying supply voltage from 0.6V to 1.3V with 0.1V steps. Based on the simulation results, lowering supply voltage is advantageous. The power dissipations of the proposed near-threshold SRMCML basic gates are almost the same as the conventional Dual-Rail MCML (DRMCML) circuits and the delay of the SRMCML is less than the DRMCML because of its single-rail scheme.
Highlights
Low power and small area are the main objectives in IC design
For the OR/NOR logic cell, the proposed Single-Rail MOS Current Mode Logic (SRMCML) can avoid the devices in series configuration, since the logic evaluation block of the SRMCML OR/NOR logic cell can be realized by only using MOS transistors in parallel
Where, R : The equivalent resistance of one branch of the load PMOS transistor ΔV : The logic swing of the output nodes, which is generated from the basic circuit Voltage swing: It is known that the pull down network in SRMCML circuits is regulated by a constant current source
Summary
Low power and small area are the main objectives in IC design. MOS Current Mode Logic (MCML) techniques are usually used for highspeed applications such as high-speed processors and Gbps multiplexers for optical transceivers (Musicer and Rabaey, 2000). Low-power Single-Rail MOS Current Mode Logic (SRMCML) circuits which operate on nearthreshold region are addressed.
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