Monolithic Process Research Articles

Electrode-to-electrode monolithic integration for high-voltage bipolar solid-state batteries based on plastic-crystal polymer electrolyte

• The EtE monolithic integration process is proposed for high-voltage bipolar SSBs. • Plastic-crystal polymer electrolyte (PCPE) was infused into a porous electrode. • The infused PCPE enables the fast Li + conduction and intimate interfacial contact. • The microstructural engineering results in enhanced performance of SSB. • The efficacy of the EtE-integration procedure is demonstrated in a bipolar SSB. Solid-state batteries (SSBs) offer a fundamental solution to mitigate the safety and reliability issues of conventional lithium-ion batteries utilizing flammable liquid electrolytes, and enable the bipolar configuration of high-voltage and high-energy storage systems. However, the conventional layer-by-layer (LbL) stacking process using individual electrolyte and electrode layers suffers from poor electrolyte–electrode contacts and challenging process complications for manufacturing multi-layer bipolar SSBs. Herein, we report an electrode-to-electrode (EtE) monolithic integration without a free-standing solid electrolyte layer for high-voltage bipolar SSBs. Positive and negative electrodes seamlessly combined with a thin solid electrolyte are fabricated by the infusion of a plastic-crystal-based polymer electrolyte (PCPE) into porous electrodes with a subsequent ultraviolet-induced solidification process. The infused PCPE in the electrodes forms continuous Li + conduction channels as well as intimate solid–solid interfaces. The thin PCPE film (∼10 μm) formed in situ on the top of the electrodes during the infusion process provides ultra-high Li + conductance (∼3.1 S cm −2 at 45 °C) between the two electrodes. SSBs are constructed via direct integration of the PCPE-infused electrodes: a unit cell-type SSB with LiNi 0.6 Co 0.2 Mn 0.2 O 2 (positive) and Li 4 Ti 5 O 12 (negative) show superior capacity (∼160 mAh g −1 ), rate capability (98 mAh g −1 at 2C), and stable cyclability (81% after 100 cycles) at 45 °C than the SSB fabricated by the conventional LbL stacking process. Moreover, a 10 V-class, bipolar SSB comprising five unit cells stacked in series is constructed via the EtE monolithic integration of multiple PCPE-infused bipolar electrodes, and its stable cycle performance is corroborated with a capacity retention of 84%. This work demonstrates that the suggested EtE integration process offers a promising strategy to addressing the interfacial contact issues of SSBs, thereby being utilized to realize scalable, low-cost, high-voltage bipolar SSBs.

Low-temperature n-type doping of insulating ultrathin amorphous indium oxide using H plasma-assisted annealing

Low-temperature process compatibility is a key factor in successfully constructing additional functional circuits on top of pre-existing circuitry without corrupting characteristics thereof, a technique that typically requires die-to-die (wafer-to-wafer) stacking and interconnecting. And against thermal annealing, which is mandatory and is possible only globally for activating amorphous oxide semiconductors, the selective control of electrical characteristics of the oxide thin-films for integrated circuit applications is challenging. Here, a low-temperature process that enables n-type doping of the designed region of insulating In2O3 thin-film is demonstrated. A short hydrogen plasma treatment followed by low-temperature annealing is used to increase interstitial and substitutional hydrogen associated bond states creating shallow donor levels in the insulating In2O3 surface to transform the thin-film into an n-type semiconductor. As a result, an In2O3 thin-film transistor with a high on/off current ratio (>108), a field-effect mobility of 3.8 cm2 V−1 s−1, and a threshold voltage of ∼3.0 V has been developed. Compared to performing just thermal annealing, the H-plasma assisted annealing process resulted in an n-type In2O3 thin-film transistor showing similar characteristics, while the processing time was reduced by ∼1/3 and the plasma-untreated area still remained insulating. With further development, the hydrogen plasma doping process may make possible a monolithic planar process technology for amorphous oxide semiconductors.

A Thermopile Infrared Sensor Array Pixel Monolithically Integrated with an NMOS Switch.

In this article, we present the design, fabrication, and characterization of a thermopile infrared sensor array (TISA) pixel. This TISA pixel is composed of a dual-layer p+/n- poly-Si thermopile with a closed membrane and an n-channel metal oxide semiconductor (NMOS) switch. To address the challenges in fabrication through the 3D integration method, the anode of the thermopile is connected to the drain of the NMOS, both of which are fabricated on the same bulk wafer using a CMOS compatible monolithic integration process. During a single process sequence, deposition, etching, lithography, and ion implantation steps are appropriately combined to fabricate the thermopile and the NMOS simultaneously. At the same time as ensuring high thermoelectric characteristics of the dual-layer p+/n- poly-Si thermopile, the basic switching functions of NMOS are achieved. Compared with a separate thermopile, the experimental results show that the thermopile integrated with the NMOS maintains a quick response, high sensitivity and high reliability. In addition, the NMOS employed as a switch can effectively and quickly control the readout of the thermopile sensing signal through the voltage, both on and off, at the gate of NMOS. Thus, such a TISA pixel fabricated by the monolithic CMOS-compatible integration approach is low-cost and high-performance, and can be applied in arrays for high-volume production.

Monolithic edge-cladding process for the elliptical disk of N31-type Nd-doped high-power laser glass

Abstract This paper investigates the monolithic edge-cladding process for the elliptical disk of N31-type Nd-doped phosphate laser glass, which will be utilized under liquid cooling conditions for high-power laser systems. The thermal stress, interface bubbles and residual reflectivity, which are due to high-temperature casting and bonding during the monolithic edge-cladding process, are simulated and determined. The applied mould is optimized to a rectangular cavity mould, and the casting temperature is optimized to 1000°C. The resulting lower bubble density makes the mean residual reflectivity as low as 6.75 × 10−5, which is enough to suppress the amplified spontaneous emission generated in the Nd-glass disk, and the resulting maximum optical retardation is converged to 10.2–13.3 nm/cm, which is a favourable base for fine annealing to achieve the stress specification of less than or equal to 5 nm/cm. After fine annealing at the optimized 520°C, the maximum optical retardation is as low as 4.8 nm/cm, and the minimum transmitted wavefront peak-to-valley value is 0.222 wavelength (632.8 nm). An N31 elliptical disk with the size of 194 mm × 102 mm × 40 mm can be successfully cladded by the optimized monolithic edge-cladding process, whose edge-cladded disk with the size of 200 mm × 108 mm × 40 mm can achieve laser gain one-third higher than that of an N21-type disk of the same size.

A Test IC for Wafer-Level Characterization of an IntraCMOS-MEMS Fabrication Process

Monitoring of fabrication processes and the measurement of the electrical and mechanical properties of materials and devices at the silicon-wafer level are of vital importance on integrated system technologies. In this work, a test integrated circuit (IC) for the development of an IntraCMOS-MEMS fabrication process is presented. The test devices contained in the test IC are designed in such a way that 1) they can be used in CMOS-MEMS fabrication technologies using different materials, 2) take into account the capabilities of the manufacturing infrastructure, and 3) consider the selected integrated fabrication scheme; thus, any monolithic CMOS-MEMS process can be evaluated before, during and after the fabrication. The acquired data from the test devices will be useful to identify possible electrical and/or mechanical variations, in the properties of the materials used and in the performance characteristics of the devices, due to the fabrication process. The information acquired will help to adjust the simulation routines and the analytical modeling expressions. Finally, using the infrastructure of the MEMS Innovation Laboratory (LIMEMS-INAOE Mexico) preliminary experimental results are presented.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Monolithic processing of a layered flexible robotic actuator film for kinetic electronics

Low-invasive soft robotic techniques can potentially be used for developing next-generation body–machine interfaces. Most soft robots require complicated fabrication processes involving 3D printing and bonding/assembling. In this letter, we describe a monolithic soft microrobot fabrication process for the mass production of soft film robots with a complex structure by simple 2D processing of a robotic actuator film. The 45 µg/mm2 lightweight film robot can be driven at a voltage of CMOS compatible 5 V with 0.15 mm−1 large curvature changes; it can generate a force 5.7 times greater than its self-weight. In a durability test, actuation could be carried out over 8000 times without degradation. To further demonstrate this technique, three types of film robots with multiple degrees of freedom and a moving illuminator robot were fabricated. This technique can easily integrate various electrical circuits developed in the past to robotic systems and can be used for developing advanced wearable sensing devices; it can be called “Kinetic electronics”.

Decomposing Monolithic Processes in a Process Algebra with Multi-actions

A monolithic process is a single recursive equation with data parameters, which only uses non-determinism, action prefixing, and recursion. We present a technique that decomposes such a monolithic process into multiple processes where each process defines behaviour for a subset of the parameters of the monolithic process. For this decomposition we can show that a composition of these processes is strongly bisimilar to the monolithic process under a suitable synchronisation context. Minimising the resulting processes before determining their composition can be used to derive a state space that is smaller than the one obtained by a monolithic exploration. We apply the decomposition technique to several specifications to show that this works in practice. Finally, we prove that state invariants can be used to further improve the effectiveness of this decomposition technique.

A Sensitivity Controllable Thermopile Infrared Sensor by Monolithic Integration of a N-channel Metal Oxide Semiconductor

We report a sensitivity controllable infrared (IR) sensor composed of a thermopile and a n-channel metal oxide semiconductor (NMOS). In the sensor, the cathode of the thermopile is connected with the gate of NMOS. Such a sensor is fabricated by using a CMOS-compatible monolithic integration process. Compared with the separate thermopile IR sensor, sensitivity of the thermopile IR sensor integrated with NMOS can be remarkably enhanced by 357%. In addition, the drain bias voltage of the NMOS can be employed as a quick-response switch. The fabrication process of this device is quite simple and compatible with CMOS processes, thus such a thermopile IR sensor integrated with NMOS is low-cost and suitable for mass production. Moreover, the integration approach can be further applied to develop thermopile arrays for high-resolution imaging.

Additive manufacturing of TiB2-containing CoCrFeMnNi high-entropy alloy matrix composites with high density and enhanced mechanical properties

Near-fully dense CoCrFeMnNi high-entropy alloy (HEA) matrix composites reinforced with 5 wt% TiB2 nanoparticles were successfully additively manufactured via the laser-engineered net shaping technique. Compared to the monolithic CoCrFeMnNi printing process, a higher energy density input is shown to produce a synergic combination of Marangoni flow and capillary force in the laser-generated melt pool. It facilitates the enhancement of wettability, and hence a more uniform distribution of the reinforcement material and a high degree of densification of 99.72%, which are able to delay the early fracture of the material. The as-deposited composites exhibit improved yield strength, surpassing that of the monolithic HEA by 42%. The enhanced strength is mainly ascribed to dispersion strengthening. Besides, the refined grain size, the increased dislocation density, and the additional load transfer effect also contribute to the strength enhancement. Furthermore, the wear resistance properties of the CoCrFeMnNi/TiB2 composite are also shown to be superior to those of the CoCrFeMnNi, indicating a decrease in friction coefficient by 22.4%. The enhanced tribological properties are attributed to the synergic effect of high-hardness and self-lubrication of TiB2 nanoparticles. The findings provide guidelines for achieving high-performance HEA-matrix composites.

A new characterization approach to study the mechanical behavior of silicon nanowires

This work proposes a new approach to characterize the mechanical properties of nanowires based on a combination of nanomechanical measurements and models. Silicon nanowires with a critical dimension of 90 nm and a length of 8 μm obtained through a monolithic process are characterized through in-situ three-point bending tests. A nonlinear nanomechanical model is developed to evaluate the mechanical behavior of nanowires. In this model, the intrinsic stress and surface parameters are examined based on Raman spectroscopy measurements and molecular dynamics simulations, respectively. This work demonstrates a new approach to measure the mechanical properties of Si nanowires by considering the surface effect and intrinsic stresses. The presented technique can be used to address the existing discrepancies between numerical estimations and experimental measurements on the modulus of elasticity of silicon nanowires.

Multielement Ring Array Based on Minute Size PMUTs for High Acoustic Pressure and Tunable Focus Depth.

This paper presents a multielement annular ring ultrasound transducer formed by individual high-frequency PMUTs (17.5 MHz in air and 8.7 MHz in liquid) intended for high-precision axial focalization and high-performance ultrasound imaging. The prototype has five independent multielement rings fabricated by a monolithic process over CMOS, allowing for a very compact and robust design. Crosstalk between rings is under 56 dB, which guarantees an efficient beam focusing on a range between 1.4 mm and 67 µm. The presented PMUT-on-CMOS annular array with an overall diameter down to 669 µm achieves an output pressure in liquid of 4.84 kPa/V/mm2 at 1.5 mm away from the array when the five channels are excited together, which is the largest reported for PMUTs. Pulse-echo experiments towards high-resolution imaging are demonstrated using the central ring as a receiver. With an equivalent diameter of 149 µm, this central ring provides high receiving sensitivity, 441.6 nV/Pa, higher than that of commercial hydrophones with equivalent size. A 1D ultrasound image using two channels is demonstrated, with maximum received signals of 7 mVpp when a nonintegrated amplifier is used, demonstrating the ultrasound imaging capabilities.

Monolithic optical microlithography of high-density elastic circuits.

Polymeric electronic materials have enabled soft and stretchable electronics. However, the lack of a universal micro/nanofabrication method for skin-like and elastic circuits results in low device density and limited parallel signal recording and processing ability relative to silicon-based devices. We present a monolithic optical microlithographic process that directly micropatterns a set of elastic electronic materials by sequential ultraviolet light-triggered solubility modulation. We fabricated transistors with channel lengths of 2 micrometers at a density of 42,000 transistors per square centimeter. We fabricated elastic circuits including an XOR gate and a half adder, both of which are essential components for an arithmetic logic unit. Our process offers a route to realize wafer-level fabrication of complex, high-density, and multilayered elastic circuits with performance rivaling that of their rigid counterparts.

Fatigue behavior of steel fiber reinforced concrete composite girder under high cycle negative bending action

Tensile concrete crack is a critical factor in the negative flexural region of a steel–concrete composite girder, which could influence the entire structural safety and durability dramatically. The steel fiber reinforced concrete (SFRC) has been utilized for constraining these cracks because of its good tensile performance and low cost in practice. But the practical application of SFRC is still hindered by the unclear fatigue performance of SFRC composite girder. To this end, four 3.3 m-long composite girder tests were executed for investigating the static and cyclic effects of SFRC and connector arrangement. About 3 million load cycles with a monolithic ultimate loading process were applied on each specimen. Generally, the fatigue load cycles in tests resulted in about 10–30% reduction of girders’ global bending stiffness without interlay bonding, and the effect of SFRC on it was not obvious. Even though there were more fatigue load induced cracks found on SFRC slabs than on the normal concrete slabs during loading, the SFRC crack width was smaller. Moreover, the steel–concrete interlayer slip development was found to be slower in SFRC composite girders, while arranging stud connectors in groups resulted in faster slip development. In addition, the test simulation and parametric analysis with material damage plasticity models were carried out, which showed a higher longitudinal reinforcement ratio in SFRC could further reduce fatigue damage on concrete.

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

An oxide semiconductor field-effect transistor (OSFET) using c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) exhibits extremely low off-state current (Ioff) and can be fabricated at a low process temperature that is 400°C or lower. The features indicate that the CAAC-IGZO FET is suitable for a monolithic stacking process and application to artificial intelligence (AI). This paper shows electric characteristics of the CAAC-IGZO FET and their factors.

Active‐matrix mesh electronics thin‐film‐transistor arrays for biometrics‐under‐display and biomedical applications

AbstractA monolithic manufacturing process is presented for the realization of active‐matrix meshed thin‐film‐transistor (TFT) arrays on foil with physical voids between pixels, realizing membrane‐like electronic arrays. The process is scalable to large‐area substrates and enables (improved performance of) biometrics‐under‐display applications. Moreover, membrane‐like TFT arrays provide opportunities for the use of TFT technology, and broader large‐area thin‐film electronics, in new applications in the domain of biomedical electronics, as demonstrated by example use cases of in vivo electrophysiology of the brain as well as in vitro electrophysiology in smart microwell plates.

4‐3: Distinguished Paper: IGZO TFT Arrays for Biometrics‐Under‐Display and Biomedical Applications

This paper presents a monolithic manufacturing process to realize active‐matrix meshed TFT arrays on foil with physical voids between pixels, realizing membrane‐like structures for use in biometrics‐under‐display applications. Moreover, however, the concept enables new applications in the biomedical electronics domain.

An innovative MEMs peizo speaker

MEMs micro-speaker development has trailed behind MEMs microphone development by over two decades due to fabrication and acoustical challenges. While MEMs microphones only need to respond to minuscule displacement, generating sound energy requires both motor force and far higher volume velocity of the transducer mechanism. Recent development of a full bandwidth piezo-MEMs micro-speaker with a silicon diaphragm creates a rigid, light, fast responding transducer with high resistance to humidity and low thermal expansion. Fabricated using a monolithic MEMS semiconductor process eliminates calibration and driver matching. 20 Hz to 20kHz frequency response is delivered in occluded earbud, IEM, and hearing aid applications. The 20 kHz resonance peak provides a smoothly increasing response in the upper octaves. This extra amplitude allows for a significant increase in hearing aid gain and bandwidth over balanced armature transducers. The device is packaged in both top- and side-fire port configurations with earbud EVKs currently shipping. Integration of the amp, on the package substrate or SiP module, opens possibilities for more compact devices, longer battery life, lower cost, and more robust construction. The combination of audio fidelity, size, and speaker to speaker uniformity is not possible with traditional voice coil or hybrid MEMS approaches.

Controlling the Flow of Distracting Information in Working Memory

Visual working memory (WM) must maintain relevant information, despite the constant influx of both relevant and irrelevant information. Attentional control mechanisms help determine which of this new information gets access to our capacity-limited WM system. Previous work has treated attentional control as a monolithic process-either distractors capture attention or they are suppressed. Here, we provide evidence that attentional capture may instead be broken down into at least two distinct subcomponent processes: (1) Spatial capture, which refers to when spatial attention shifts towards the location of irrelevant stimuli and (2) item-based capture, which refers to when item-based WM representations of irrelevant stimuli are formed. To dissociate these two subcomponent processes of attentional capture, we utilized a series of electroencephalography components that track WM maintenance (contralateral delay activity), suppression (distractor positivity), item individuation (N2pc), and spatial attention (lateralized alpha power). We show that new, relevant information (i.e., a task-relevant distractor) triggers both spatial and item-based capture. Irrelevant distractors, however, only trigger spatial capture from which ongoing WM representations can recover more easily. This fractionation of attentional capture into distinct subcomponent processes provides a refined framework for understanding how distracting stimuli affect attention and WM.

Monolithic fabrication of vertical silicon nanowire gas sensor with a top porous copper electrode using glancing angle deposition

Vertical Si nanowire (SiNW) gas sensor with a top porous electrode (TPE) has been reported as a highly sensitive, small footprint, and mass-producible gas sensor platform. In this article, a monolithic fabrication process for a vertical SiNW gas sensor using glancing angle deposition (GLAD) was proposed as a simple, low-cost, and large-area fabrication method, and the performance of the fabricated vertical SiNW gas sensor was evaluated via relative humidity measurement. The 1,000 nm length vertical SiNWs were uniformly fabricated on a 4-inch silicon wafer via GLAD at an oblique angle of 85° and a substrate rotation speed of 5 rpm. A Cu TPE was also fabricated via sequential GLAD without substrate rotation to realize the wafer-level vertical gas sensor from which multiple 2 × 2 cm2 vertical SiNW gas sensors were obtained by dicing. To optimize the Cu TPE fabrication process, the effects of oblique angle and deposition thickness on the conductivity and porosity of the TPE were examined; subsequently, an oblique angle of 65° and a thickness of 100 nm were selected as the optimum conditions when considering humidity measurement sensitivity.