Monolithic Integration Technology Research Articles

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Electroless deposition of high-uniformity nickel microbumps with ultrahigh resolution of 8 μm pitch for monolithic Micro-LED display

Micro-light-emitting diode (Micro-LED) displays have attracted growing attention due to their unsurpassed properties that satisfy the requirements of reality/virtual reality (AR/VR) displays. A crucial procedure of monolithic integration technology in high-density microdisplays is the interconnection process, which is intimately associated with the quality of the display device. Microfluidic electroless interconnection (MELI), an innovative low-temperature and pressure-free chip-stacking approach that eliminates the warpage-induced issues and cracking damage of the chip caused by thermo-compression bonding (TCB), holds great promise as a technology for establishing interconnections between the CMOS driver and Micro-LED. However, the requirement for the consistency of the microbump arrays and the risk of creating bridges is significantly intensified with smaller gaps in stacked chips, which restricts the application range of MELI to high-density interconnects. This paper analyzes the feasibility of further lowering the stand-off height of stacked chips in ultrafine pitch interconnects by optimizing the bump preparation process. The plasma modification time and surfactant concentration during the bump preparation process have been investigated. The result indicated that microbump arrays with a uniformity of less than 3% could be successfully manufactured by employing a 7-min plasma treatment and incorporating optimal surfactants, which catalyzes the implementation of the subsequent vertical interconnection process and eventually enhances yields of Micro-LEDs.

All-Silicon Photoelectric Biosensor on Chip Based on Silicon Nitride Waveguide with Low Loss.

Compared to the widely used compound semiconductor photoelectric sensors, all-silicon photoelectric sensors have the advantage of easy mass production because they are compatible with the complementary metal-oxide-semiconductor (CMOS) fabrication technique. In this paper, we propose an all-silicon photoelectric biosensor with a simple process and that is integrated, miniature, and with low loss. This biosensor is based on monolithic integration technology, and its light source is a PN junction cascaded polysilicon nanostructure. The detection device utilizes a simple refractive index sensing method. According to our simulation, when the refractive index of the detected material is more than 1.52, evanescent wave intensity decreases with the growth of the refractive index. Thus, refractive index sensing can be achieved. Moreover, it was also shown that, compared to a slab waveguide, the embedded waveguide designed in this paper has a lower loss. With these features, our all-silicon photoelectric biosensor (ASPB) demonstrates its potential in the application of handheld biosensors.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Synchronization of frequency combs by optical injection.

Optical frequency combs based on semiconductor lasers are a promising technology for monolithic integration of dual-comb spectrometers. However, the stabilization of offset frequency fceo remains a challenging feat due the lack of octave-spanning spectra. In a dual-comb configuration, the uncorrelated jitter of the offset frequencies leads to a non-periodic signal resulting in broadened beatnotes with a limited signal-to-noise ratio (SNR). Hence, expensive data acquisition schemes and complex signal processing are currently required. Here, we show that the offset frequencies of two frequency combs can be synchronized by optical injection locking, which allows full phase-stabilization when combined with electrical injection locking of both repetition frequencies frep. A single comb line isolated via an optical Vernier filter serves as Master oscillator for injection locking. The resulting dual-comb signal is periodic and stable over thousands of periods. This enables coherent averaging using analog electronics, which increases the SNR and reduces the data size by one and three orders of magnitude, respectively. The presented method will enable fully phase-stabilized dual-comb spectrometers by leveraging on integrated optical filters and provides access for comparing and stabilizing fceo to narrow-linewidth optical references.

High-Efficiency D-Band Monolithically Integrated GaN SBD-Based Frequency Doubler With High Power Handling Capability

A high-efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula> -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W.

1300 nm Semiconductor Optical Amplifier Compatible With an InP Monolithic Active/Passive Integration Technology

In monolithic photonic integrated circuits (PICs), an optimized active/passive integration is needed to provide efficient coupling and low amount of interface reflections between amplifiers and passive components. A 1300 nm semiconductor optical amplifier (SOA) on InP substrate and optimized for butt-joint reflections is investigated. Material performance were assessed from measurements of broad area lasers. Room temperature operation reveals 1.2 W single facet output power with threshold current around 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per well. Characteristic temperatures of T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 75 K and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> = 294 K were obtained. A compact model description of the SOA, suitable for the design of PICs and rate equation analysis, was applied to parametrize the unsaturated gain measurements. Current injection efficiency of 0.65, transparency carrier density of 0.57 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> , and free carrier absorption losses up to 15 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> were extracted from fitting the data. The model is verified with measurements of optical gain saturation. A modal gain of 15 dB for a 600 μm long narrow ridge SOA leads to output saturation power higher than 30 mW at 7 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This building block contributes to the development of an InP monolithic integration technology in the 1300 nm range, which can enable the use of photonic integrated circuits in many kind of applications.

Highly sensitive SWIR photodetector using carbon nanotube thin film transistor gated by quantum dots heterojunction

Low-dimensional semiconductors have been considered excellent materials to construct photodetectors for infrared detection with an easy process and excellent compatibility but suffer from low detectivity mainly owing to the poor light absorption of the ultra-thin body. Here, we demonstrate a thin film transistor (TFT) based short-wave infrared photodetector consisting of a carbon nanotube (CNT) TFT gated by a PbS colloidal quantum dots (CQDs) based heterojunction. The thick PbS CQDs' film efficiently absorbs infrared light and then excites and separates electron–hole pairs to generate a photovoltage at the pn heterojunction of the PbS CQDs/ZnO film. The photovoltage is further amplified and transduced in situ by the CNT TFT under the heterojunction, and then the detector featured a specific detectivity of 5.6 × 1013 Jones under 1300 nm illumination and a fast response of the sub-ms level (0.57 ms). The CQDs based heterojunction gating TFT represents a universal architecture for highly sensitive low-dimensional semiconductor based infrared photodetectors, competitive with state-of-the-art epitaxial semiconductors and enabling monolithic integration technology.

InP-Based Butt-Joint Coupled Waveguide Photodiodes Integrated With Various Functions for 100 GBaud Coherent Detection

This paper reports on the performance of an InP-based butt-joint (BJ) coupled waveguide photodiode (PD) for 100 GBaud coherent detection. We adopt a dual-layer absorber comprised of p- and i-type GaInAs absorption layers to enhance the advantage of BJ coupled waveguide PDs which overcome the tradeoff between high responsivity and wide bandwidth. As a result, a responsivity as high as 0.90 A/W over the C-band and a wide 3 dB bandwidth of 71 GHz have been successfully obtained at a reverse bias voltage of 2.5 V. Towards the realization of compact coherent modules without complicated assembly processes, we have also fabricated a compact photonic integrated circuit (PIC) chip (Chip size: 2.6 × 4.1 mm) configured by 12 BJ coupled waveguide PDs and various optical functions, such as 90° hybrids and variable optical attenuators (VOAs) through the InP-based monolithic integration technology. An integrated coherent transmitter-receiver optical sub-assembly (IC-TROSA) employing the PIC has exhibited receiver performance sufficient for 100 GBaud coherent detection.

Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects

Monolithic 3D integration technology has emerged as an alternative candidate to conventional transistor scaling. Unlike conventional processes where multiple metal layers are fabricated above a single transistor layer, monolithic 3D technology enables multiple transistor layers above a single substrate. By providing vertical interconnects with physical dimensions similar to conventional metal vias, monolithic 3D technology enables unprecedented integration density and high bandwidth communication, which plays a critical role for various data-centric applications. Despite growing number of research efforts on various aspects of monolithic 3D integration, commercial monolithic 3D ICs do not yet exist. This tutorial brief provides a concise overview of monolithic 3D technology, highlighting important results and future prospects. Several applications that can potentially benefit from this technology are also discussed.

Development of 340-GHz Transceiver Front End Based on GaAs Monolithic Integration Technology for THz Active Imaging Array

Frequency multipliers and mixers based on Schottky barrier diodes (SBDs) are widely used in terahertz (THz) imaging applications. However, they still face obstacles, such as poor performance consistency caused by discrete flip-chip diodes, as well as low efficiency and large receiving noise temperature. It is very hard to meet the requirement of multiple channels in THz imaging array. In order to solve this problem, 12-μm-thick gallium arsenide (GaAs) monolithic integrated technology was adopted. In the process, the diode chip shared the same GaAs substrate with the transmission line, and the diode’s pads were seamlessly connected to the transmission line without using silver glue. A three-dimensional (3D) electromagnetic (EM) model of the diode chip was established in Ansys High Frequency Structure Simulator (HFSS) to accurately characterize the parasitic parameters. Based on the model, by quantitatively analyzing the influence of the surface channel width and the diode anode junction area on the best efficiency, the final parameters and dimensions of the diode were further optimized and determined. Finally, three 0.34 THz triplers and subharmonic mixers (SHMs) were manufactured, assembled, and measured for demonstration, all of which comprised a waveguide housing, a GaAs circuit integrated with diodes, and other external connectors. Experimental results show that all the triplers and SHMs had great performance consistency. Typically, when the input power was 100 mW, the output power of the THz tripler was greater than 1 mW in the frequency range of 324 GHz to 352 GHz, and a peak efficiency of 6.8% was achieved at 338 GHz. The THz SHM exhibited quite a low double sideband (DSB) noise temperature of 900~1500 K and a DSB conversion loss of 6.9~9 dB over the frequency range of 325~352 GHz. It is indicated that the GaAs monolithic integrated process, diodes modeling, and circuits simulation method in this paper provide an effective way to design THz frequency multiplier and mixer circuits.

Pseudo-2D superconducting quantum computing circuit for the surface code: proposal and preliminary tests

Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.

Development of a Wideband 220-GHz Subharmonic Mixer Based on GaAs Monolithic Integration Technology

A wideband 220 GHz subharmonic mixer based on monolithic integration technology is proposed in this paper. It features 12 Mm-thick GaAs membrane with anti-parallel Schottky diodes working at THz band monolithically integrated on the membrane. The optimization principles of low-parastics Schottky diodes and the fabrication process of GaAs MMIC membrane diodes are elaborated. To realize optimum performances of the mixer, the dimensions of the integrated diodes and the matching network are optimized with harmonic balance simulation and load-pull techniques. An IF low pass filter with compact microstrip resonance cell (CMRC) configuration and an improved perpendicular coax-to-microstrip connection are used to realize wide IF band. The measured results show that the single sideband (SSB) conversion loss of this mixer is less than 10.5 dB from 185 to 255 GHz with fixed IF of 1 GHz, while the double sideband (DSB) noise temperature is better than 1400 K in this frequency range. Using fixed local oscillator (LO) frequency of 110 GHz, the measured SSB conversion loss is 7.4-10.7 dB within 185-255 GHz, indicating the good performances of the mixer with IF from DC to 35 GHz. The GaAs monolithic integration technology provides an approach for massive manufacturing of identical circuits and the proposed mixer with wideband characteristics will be applied in 220 GHz imaging systems in the near future.

Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs

The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect $RC$ parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by intertier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support

We present a novel 3D-SRAM cells using a monolithic 3D integration technology for realizing both robustness of the cell and in-memory Boolean logic computing capability. The proposed two-layer cell designs make use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, and XNOR/XOR) or enable content addressability without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes, and we evaluate the energy efficiency of our proposed design. We show that the assist techniques improve SRAM read stability by $2.2\times $ and increase the write margin by 17.6% while staying within the SRAM footprint. By the virtue of increased robustness, the cell enables seamless operation at lower supply voltages; and thereby, ensures energy efficiency. Energy delay product reduces by $1.6\times $ over standard 6T SRAM with a faster data access. When computing bulk In-memory operations, $6.5\times $ energy saving is achieved as compared to computing outside the memory system.

Bent cantilever radio frequency microelectromechanical system power detector with improved linearity up to 1 W

This study reports a bent cantilever radio frequency microelectromechanical system power detector with improved linearity up to 1 W. The proposed device employs an upward bent cantilever for power detection. The novelty of this structure is that the bend of this kind in cantilever can realize the compensation for non-linear saturation at high power level effectively. As a result, the linearity will be improved on the condition of high power detection. An equivalent circuit model of mechanical principle is established to analyse the bent cantilever behaviour. The whole device is fabricated using GaAs microwave monolithic integrated circuit technology. The bent cantilever is constructed to overcome the stress gradient during deep etching releasing process. Measurement results prove the improved linearity from 100 mW to 1 W and the corresponding sensitivity is 2.8 aF/mW at 10 GHz.

A Micro-Machined Phase Discriminator With Improved Power Capacity on C-Band and X-Band

This paper reports a micro-machined phase discriminator with improved power capacity on C-band and X-band. The proposed phase discriminator is processed using GaAs microwave monolithic integrated circuit technology. First, a dual-frequency power combiner is designed to extend the working frequency band. Second, a sandwich-type thermoelectric power sensor is adopted to improve the power capacity. The unique device consequently has the advantages of ultra-wide band and high power capacity. The measurement results show good S-parameters within 6-12 GHz. The sensitivities among all measured frequency points are better than 42.3 μV/deg at 23 dBm, 82.5 μV/deg at 27 dBm, and 167.3 μV/deg at 30 dBm, respectively. What is more, the experiment of response time shows that the rise time is about 617.25 μs, while the fall time is about 304.69 μs.

59‐3: Distinguished Paper: Wafer Scale Hybrid Monolithic Integration of Si‐based IC and III‐V Epilayers ‐ a Mass Manufacturable Approach for Active Matrix micro‐LED Displays

JBD has developed its unique wafer‐level mass manufacturable approach of monolithic hybrid integration of compound semiconductor functional device arrays on Si ICs, which enables the fabrication of hybrid chips with large device array and ultra‐fine pitch of a few micrometers. Red, green and blue active matrix micro‐LED (AMµLED) micro displays of VGA format with 1270ppi pixel resolution and 256 grayscales were successfully fabricated using JBD's monolithic hybrid integration technology. Further integration of a micro‐reflector array on the micro‐LED array significantly improves the emission directionality of the AMµLED micro display, resulting in an ultra‐high brightness of 3x10 6 nits for green AMµLED micro displays. The resultant monochromatic micro‐LED micro displays exhibit improved device performance compared to other micro display technologies and have great potentials in applications such as portable projectors and near‐to‐eye projection for augmented reality (AR). More importantly, the wafer‐scale monolithic hybrid integration technology offers a clear path for large volume, low cost mass production of hybrid opto‐electronic integrated circuit (OEIC) chips.

Wafer‐scale monolithic hybrid integration of Si‐based IC and III–V epi‐layers—A mass manufacturable approach for active matrix micro‐LED micro‐displays

AbstractHybridization of silicon integrated circuits (ICs) with compound semiconductor device arrays are crucial for making functional hybrid chips, which are found to have enormous applications in many areas. Although widely used in manufacturing hybrid chips, the flip‐chip technology suffers from several limitations that are difficult to overcome, especially when the demand is raised to make functional hybrid chips with higher device array density without sacrificing the chip footprint. To address those issues, Beida Jade Bird Display Limited has developed its unique wafer‐level monolithic hybrid integration technology and demonstrated its advantages in making large‐scale hybrid integration of functional device arrays on Si IC wafers. Active matrix micro‐light‐emitting diode micro‐displays with a resolution of 5000+ pixel per inch were successfully fabricated using Beida Jade Bird Display Limited's monolithic hybrid integration technology. The general fabrication method is described, and the result is presented in this paper. The fabricated monochromatic micro‐light‐emitting diode micro‐displays exhibit improved device performance than do other micro‐display technologies and have great potentials in applications such as portable projectors and near‐to‐eye projection for augmented reality. More importantly, the wafer‐scale monolithic hybrid integration technology offers a clear path for low‐cost mass production of hybrid optoelectronic IC chips.

Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons

Because of fabrication compatibility to current semiconductor technology, three-dimensional integrated circuits (3D-ICs) offer promising near-term solutions for maintaining Moore’s Law. 3D-ICs proffer high system speeds, massively parallel processing, low power consumption, and their high densities result in small footprints. In this paper, a novel 3D neuromorphic IC architecture which combines monolithic 3D integration and a synaptic array based on vertical resistive random-access memory structure (V-RRAM) is proposed. To analyze the electrical characteristics of the proposed synaptic array, a concise equivalent circuit model of the system is developed, and analytical calculations for each parameter of the equivalent circuit are provided. Moreover, a novel signal intensity encoding neuron design that can directly convert analog signal into a spiking waveform sequence is proposed and analyzed. A feasible 3D neuromorphic computing architecture is demonstrated. Applying the monolithic 3D integration technology on neuromorphic computing system hardware implementation can reduce the power consumption by 50%, and shrink die areas by 35%.