Monolithic Integrated Circuit Research Articles

Thermal design of a solid-state power amplifier at Q-band

Abstract It is very difficult to cool a new solid-state power amplifier at Q-band, which is composed of some high-power monolithic millimeter-wave integrated circuit chips. Cu/Diamond carriers are used as the heat sinks of the chips, and two layers of heat pipes are sealed in the chassis to reduce the thermal resistance of the amplifier. The thermal design scheme is proved useful by simulating Flotherm and the temperature data from the infrared imager. The study provides an available way for the thermal design of a solid-state power amplifier.

Thermal modelling and layout optimization of GaN half-bridge IC with integrated drivers and power HEMTs

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization.

A 220 GHz GaN‐based monolithic integrated frequency doubler delivering over 0.25 W output power

AbstractA 220 GHz GaN‐based monolithic integrated frequency doubler with high continuous‐wave output power has been developed. The doubler achieves improved heat dissipation by establishing the terahertz (THz) monolithic integrated circuit topology with GaN Schottky barrier diodes integrated on a high thermal conductivity SiC substrate. It features six anodes to enhance the power‐handling capabilities. A refractory Schottky metal stack is adopted for better thermal stability. The doubler realizes satisfactory performance by introducing the suspended microstrip and an all‐in‐one output structure. For verification, a prototype of the proposed frequency doubler was fabricated and tested. Measured results show that the proposed doubler produces a continuous‐wave output power of 255 mW at 220 GHz with an efficiency of 14.6%, exhibiting excellent potential for powerful THz sources.

Gallium arsenide octave-bandwidth microwave voltage-controlled oscillator having discrete varicap

Modern reconfigurable communication systems demand microwave voltage-controlled oscillators (VCOs) possessing an octave-wide bandwidth. Many advanced applications require also a low phase noise and a low current consumption for such VCOs. To meet an octave-bandwidth specification in combination with a low phase noise and a low current consumption it is desirable to implement a microwave monolithic integrated circuit (MMIC) technology. In-house gallium arsenide (GaAs) MMIC technology is implemented to build VCOs in this work. At the same time, in order to achieve a high-Q wide frequency tuning range, we implemented also a discrete variable capacitance diode (varicap). The discrete varicap is stacked above MMIC oscillator chip. A vertical design structure of the discrete varicap guarantees a high overlap capacitance ratio (K>20) along with reduced affect of the parasitic reactance. A high overlap capacitance ratio is needed for an octave-wide frequency tuning, while reduced affect of the parasitic reactance increases Q-factor of the VCO resonator. Hence, a sequential integration of the discrete varicap over monolithic oscillator chip resolves referred tough challenges in the design of VCO. Integrated VCO is finally packaged as a surface-mount device (SMD). At that SMD ceramic package is sealed with the metal lid. The oscillator circuitry is based on the conventional negative resistance approach with a positive feedback realized by common-source capacitance. An active element of the oscillator is a pseudomorphic high electron-mobility transistor (pHEMT). The gate length of a transistor is 0.15 µm. The width of the gate varies from 240 µm to 360 µm depending on working frequencies of the VCO. The varicap is built on the GaAs epitaxial heterostructure having customized gradient doping profile with abrupt junction. Nonlinear behavioral model of the varicap is extracted from the diode measurements and is further used for VCO simulation. Two types of VCO have been designed, fabricated and tested. First (second) type of VCO provides a tuning range from 5 to 10 GHz (from 10 GHz to 20 GHz), respectively. The measurement results demonstrate an output power of 3.9 dBm; a current consumption of 30 mA at a supply voltage of 5 V; a phase noise of minus 90 dBc/Hz at 100 kHz offset (minus 85 dBc/Hz at 100 kHz offset) for the first (second) type of VCO, respectively.

The main directions of enhancement of digital antenna arrays

The development of modern radio electronic systems causes an increase in the requirements for the parameters of antenna devices (AU) and causes the transition from previously used mirror antennas and passive phased array antennas (FAA) to active FAA (AFAA), the considerable advantage of which is a significant reduction in energy losses of transmitted and received signals by reducing the distance of the low-noise amplifier input and output of power amplifier to the antenna element. Further development of the AU is the transition from AFAA with analog beamforming to digital antenna arrays (DAR) with digital beamforming, the advantages of which are due to the possibility of forming multibeam receiving and transmitting radiation patterns with independent control of the direction and shape of the beams, as well as the possibility of flexible change of operating modes. The use of a DAR with two-dimensional electronic scanning provides a significant increase in the efficiency of radio-electronic systems. Thus, their use in radar provides a gain in the efficiency of using the time, energy, frequency and spatial resources of radar with CAR up to 13 times compared with radar with passive FAA and AFAA with one-dimensional scanning. The disadvantages of the DAR are the high cost and increased energy consumption due to the installation of active elements in each transceiver channel, as well as the long time required to create new products, associated with a large amount of software and a complex structure for building a CAR. To overcome these disadvantages, manufacturers of antenna arrays and developers of the radio-electronic element base are creating new technical solutions. The main directions of development of technologies for the production of DAR functional devices that reduce the cost and reduce the time needed to create new products are shown: the development of common modules that allow you to create scalable DAR, increasing the integration of microwave monolithic integrated circuits with the placement of the maximum number of transceiver channels on one chip, increasing the integration of ASIC, including ADCs, DACs and digital signal processing devices, increasing the clock frequencies of digital functional nodes, as well as the development of circuit solutions for building nodes with low energy consumption.

IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Calls for Papers

IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Calls for Papers

Enhanced performance of Ku-band GaN MMIC PA through embedded microfluidic cooling

The impact of embedded microfluidic cooling on the performance of Ku-band gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) power amplifiers (PAs) has been studied in this work. The research demonstrates that embedded cooling can substantially lower junction temperatures, mitigate the self-heating effect, and thereby improve the electrical performance of GaN MMIC PAs. Using merely 10.4 mW of pumping power (Ppump), the technology reduces the maximum junction temperature (Tj,max) from 216.7 to 147.8 °C. Furthermore, the system enhances the saturation current by 13.8%, increases output power (Pout) and gain (Gain) by 1.8 dB, elevates the power added efficiency (PAE) by 5.9%, and improves the heat flux of last gate (Qgate) to 37.3 kW/mm2 and the heat flux of MMIC (QMMIC) over 2.6 W/mm2, while reducing the thermal resistance (Rj-c) from 2.13 to 1.26 °C/W. Additionally, there is a notable improvement of the small signal gain (S21) by 2.5 dB. Therefore, the achievements in this work indicate that embedded cooling offers a powerful technique to suppress the thermal effects on GaN MMIC PAs, consequently improving their electrical performance.

Design and Implementation of a DC to AC Power Electronics-Based Inverter that Produces Pure Sine Wave Output for Critical Engineering Applications

Power inverters play a crucial role in the field of engineering, particularly in applications where power stability is imperative. In devices such as Uninterruptible Power Supplies (UPS), the conversion of raw power to DC, subsequent filtering, and inversion to AC are executed through pure sine wave inverters. These inverters exhibit remarkable stability, making them ideal for powering sensitive equipment like data switches and Remote Terminal Units (RTUs). This study delves into the intricate process of converting DC power into a pristine sine wave signal. The heart of this power conversion lies in the utilization of the KA3525A integrated circuit (IC) in conjunction with MOSFETs of the PN55 series, supported by capacitors and resistors for effective power filtration. The KA3525A, a monolithic IC, encompasses all essential control circuits for a pulse width modulating regulator. Within this IC, a voltage reference, error amplifier, pulse width modulator, oscillator, under-voltage lockout, soft start circuit, and output driver collaborate seamlessly. The MOSFETs function as switches, synchronized with the oscillating signal from the KA3525A IC. This coordination, combined with the filter and other signal conditioning units, enables the conversion process. The design achieves the conversion of raw power into a stable pure sine wave signal of 170V AC at the H-bridge terminals, demonstrating the success of the designed approach.

Modified elliptic response bandpass filtering integrated high‐efficiency GaN MMIC power amplifier at 24–28 GHz

SummaryIn this paper, an out‐of‐band suppression enhanced high‐efficiency millimeter‐wave (mm‐wave) gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) filtering power amplifier (FPA) is presented. A modified elliptic response bandpass filtering (BPF) output matching network (OMN) is used to achieve low loss and high out‐of‐band rejection. The circuit of the presented BPF OMN is given and its synthesized method is introduced. The simulated S‐parameters show that the OMN has a low‐loss in‐band response and a desired out‐of‐band rejection performance with two transmission zeros (TZs). To demonstrate this idea, a two‐stage 24–28‐GHz GaN MMIC PA is designed and implemented in a 0.15‐μm GaN‐on‐SiC process, with a mask area of 2.4 × 1.0 mm2. Experimental results show that the realized MMIC PA achieves a small signal gain of 18.8 dB from 24 to 28 GHz with ±1.2‐dB gain flatness and 40‐dB rejection at 19.43 and 33.8 GHz. The saturated power‐added efficiency (PAE) is higher than 29% from 24 to 28 GHz, with a peak PAE of 36.3% at 27 GHz. The output power is within the range of 33.8 to 35.6 dBm in the operating band. For a 100‐MHz five‐carrier LTE signal, the PA can achieve ACLR better than −40 dBc over the band with digital predistortion.

Study on the single-event burnout mechanism of GaN MMIC power amplifiers

In this Letter, a single-event burnout (SEB) mechanism in gallium nitride (GaN) microwave monolithic integrated circuit power amplifiers with a high linear energy transfer of 78.1 MeV·cm2/mg has been investigated in detail. A typical SEB phenomenon was observed. With the aid of photon emission measurements and scanning electron microscopy, it is found that catastrophic burnout occurs in the power-stage GaN high electron mobility transistors (HEMTs) and the metal–insulator–metal (MIM) capacitors, respectively. For the GaN HEMT, the incident heavy ions will generate electron–hole pairs within it, which can gain enough energy with the transverse high electric field. The high-energy electrons will collide with the lattice near the drain electrode and induce significant electron trapping, which will result in a significant longitudinal local electric field. When a critical electric field is achieved, catastrophic burnout occurs. For the MIM capacitor, the burnout is attributed to the single-event dielectric rupture via severe impact ionization or latent tracks when heavy ions strike it.

A compact and reconfigurable C-band DGS-based power divider using RF MEMS capacitive switch

This article presents a reconfigurable and compact power divider design that utilizes a combination of defect structures in the ground plane (DGS) and capacitance loading using a unique RF MEMS switch on the sapphire substrate. The combination of these two techniques results in a reduced-size reconfigurable power divider, wherein the length of the quarter-wavelength transmission line is reduced to λ/16 from λ/4, and the higher-order harmonics are suppressed up to 40 GHz. The RF MEMS capacitive switch is designed, and its DC characteristics are simulated in coventorware. The RF characteristics of the designed power divider are simulated in Ansys HFSS 19.2. The power divider utilizing RF MEMS technology has been fabricated through surface micromachining, requiring only four masks for fabrication. According to measurement findings, insertion loss and return loss are 3.57 dB and 24.6 dB (at 4.4 GHz) and 3.82 dB and 22.06 dB (at 5.4 GHz) when the switch is on and off, respectively. The total area of the design is 3.1 mm2 (21.3% of the conventional power divider). The proposed design can suppress harmonics up to the 8th order by 10 dB. These features render it a viable option for employment in Radio Frequency Integrated Circuits (RFICs).

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70 μm pixel pitch

This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32 × 32 pixel matrix at 70 μm pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30 %. A sub-100 ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3 MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4 Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation delays across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.

Simplified Emulation of Active Load Modulation for a Millimeter-Wave GaN MMIC Doherty Power Amplifier Design

Based on large-signal simulations, this article proposes a simplified method to emulate the active load modulation between the carrier and peaking transistors in a Doherty power amplifier (DPA) design. In contrast to the conventional load–pull method, the proposed method contributes to emulating the active load modulation between the load-modulated transistors with considering their nonlinear interaction. It offers the advantages of predicting the real-world performance of the load-modulated transistors and providing the optimum load-modulation trajectories to be synthesized in a DPA design. To verify the proposed method, a two-way millimeter-wave (mmWave) gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) DPA is designed from 25.5 to 27 GHz. The measured results show that the realized MMIC DPA achieves power-added efficiency (PAE) higher than 30% at saturation, 27% at 6-dB back-off, and 21.5% at 8-dB back-off, with a saturated output power higher than 31.4 dBm across the band. When tested using a 400-MHz modulated signal with digital predistortion (DPD), the MMIC DPA shows adjacent channel power ratio (ACPR) levels better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 40 dBc over the band.

Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing

Monolithic three-dimensional (M3D) integration allows ultra-thin silicon tier stacking in a single package. The high-density stacking is acquiring interest and is becoming more popular for smaller footprint areas, shorter wirelength, higher performance, and lower power consumption than the conventional planar fabrication technologies. The physical design of M3D integrated circuits requires several design steps, such as three-dimensional (3D) placement, 3D clock-tree synthesis, 3D routing, and 3D optimization. Among these, 3D routing is significantly time consuming due to countless routing blockages. Therefore, 3D routers proposed in the literature insert monolithic interlayer vias (MIVs) and perform tier-by-tier routing in two substeps. In this article, we propose an algorithm to build a routing topology database (DB) used to construct all multilayer monolithic rectilinear Steiner minimum trees on the 3D Hanan grid. To demonstrate the effectiveness of the DB in various applications, we use the DB to construct timing-driven 3D routing topologies and perform congestion-aware global routing on 3D designs. We anticipate that the algorithm and the DB will help 3D routers reduce the runtime of the MIV insertion step and improve the quality of the 3D routing.

Systematic Study and Review of InP‐based Tera‐Hertz‐ICs Fabrication Process Technology for Beyond 5G/6G Wireless Communication Networks

Next‐generation “Beyond 5G (B5G)/6G” wireless network systems have been researched and developed for meeting the rapid growth of mobile traffic. A high‐yield fabrication process of InP‐based transistors and tera‐hertz monolithic integrated circuits with 300 GHz operation is reported, which is a candidate frequency for “Beyond 5G/6G” network systems. The main focus is on a high‐yield and reproductive fabrication process of InP‐based high electron mobility transistors (HEMTs) while revisiting previous studies. The DC and radio frequency characteristics of fabricated InP‐HEMTs from the viewpoint of integrating circuits are described. Then, high‐frequency performances of ft = 280 GHz and fmax = 860 GHz in the bias conditions of Vgs/Vds = 0.2/1.1 V with good uniformity are obtained. Finally, InP‐based 300 GHz‐band mixer and power amplifiers are introduced, to which a backside process is also applied for ensuring their stability and enhancing output power.

(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology

This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon.

An improved harmonics suppression power amplifier circuit using integrated self‐resonant capacitor for radar application

SummaryIn order to ensure that the electromagnetic compatibility and mutual interference of multiple radar network systems meet the requirements, a 55‐W gallium nitride (GaN) high harmonics suppression (HSs) high power amplifier (HPA) microwave monolithic integrated circuit (MMIC) with an operating frequency of 5.1–6.3 GHz is designed for radar network system. An HSs method using self‐resonant capacitor integrated in the output matching network of HPA is proposed to improve the HSs characteristics. The measured results show that under the condition of 100‐μs pulse width and 10% duty cycle, the HSs are greater than 48 dBc while the output power is greater than 55 W, the power gain is 21 dB, and the power additional efficiency (PAE) is 54%, which is suitable for use in radar network system. The size of the HPA is 3.55 × 4.05 mm2.

Fabrication of a Novel GaAs Thermopile Sensor for RF Amplitude Demodulation

In this letter, a novel fabrication of straight-channel RF AM demodulator based on thermopile is presented. Its structure consists mainly of CPW line fed with AM signal, resistors and thermopiles to detect the demodulated signal. The structure is fabricated using GaAs Microwave Monolithic Integrated Circuit (MMIC) technology. Experiments are implemented and the results show that this thermopile-based demodulator is able to perform demodulation of AM signal with carrier frequency of 0.01-10 GHz and signal frequency of under 5 kHz. The influence of thermopile length on the performance is also studied and the result shows that when the thermopile length gets larger, the output amplitude of the demodulated signal gets larger, but its bandwidth gets smaller. In our scenario, the length of the thermopile can be set as 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m as a tradeoff between amplitude and bandwidth. 2022-0187

A Ku-Band GaN-on-Si MMIC Power Amplifier with an Asymmetrical Output Combiner.

In this paper, a microwave monolithic integrated circuit (MMIC) high-power amplifier (HPA) for Ku-band active radar applications based on gallium nitride on silicon (GaN-on-Si) is presented. The design is based on a three-stage architecture and was implemented using the D01GH technology provided by OMMIC foundry. Details on the architecture definition and design process to maximize delivered power are provided along with stability and thermal analyses. To optimize the amplifier performance, an asymmetry was included at the output combiner. Experimental results show that the HPA achieves a 39.5 dBm pulsed-mode output power, a peak linear gain of 23 dB, a drain efficiency of 27%, and good input/output matching in the 16-19 GHz frequency range. The chip area is 5 × 3.5 mm2 and for the measurements was mounted on a custom-made module. These results demonstrate that GaN-on-Si-based Solid-State Power Amplifiers (SSPAs) can be used for the implementation of Ku-band active radars.