Monolithic IC Research Articles

A monolithic DC temperature compensation bias scheme for multistage HEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125/spl deg/C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB//spl deg/C temperature coefficient which is strictly due to HEMT device G/sub m/ variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V/sub gs/-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications.

MMIC's for an integrated RF spectrum analyzer front end

The monolithic microwave IC (MMIC) approach for the front end of an RF spectrum analyzer improves interconnection problems due to direct access to a device-under-test (DUT). This paper proposes and demonstrates novel MMIC's for a probe-type, 1-32 GHz spectrum analyzer (SPA) front end. The MMIC's are an up-converter, a variable attenuator, a switch, and a down-converter. This MMIC set utilizes novel FET cells for impedance matching, signal combinations, isolation, and impedance translation to achieve an ultra-wideband performance as well as a remarkable size reduction in an SPA front end.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A GaAs high power RF single-pole dual throw switch IC for digital-mobile communication system

Much effort has been devoted to integrate the receiving/transmitting switch since time divided multiple access (TDMA) became widely used for digital mobile communication systems. Conventional Si pin-diode switches require increased current bias as the transmit power is increased to maintain the ON state. A recently-developed GaAs monolithic switch IC can be operated with nearly zero power dissipation. However, there is distortion of the waveform as the transmit power is increased. This limits the power handling capability. Another disadvantage of the GaAs switch IC is that negative voltages are needed to control the ON and OFF states. The high-power GaAs monolithic RF switch IC reported here handles over 5W (PldB: 37dBm) with insertion loss less than 1.0 dB using a circuit to feed forward the signal to the control gate. Positive voltage switching is achieved by integrating large coupling capacitors using high dielectric material, barium strontium titanate (BST), at inputs and outputs. The RF single-pole double-throw (SPDT) switch IC is mounted in an SSO10 package, where better than 25 dB isolation is achieved at a frequency of 1 GHz. >

An 800-MHz monolithic GaAs HBT serrodyne modulator

An 800-MHz monolithic mixed-signal serrodyne modulator IC has been developed in a GaAs/AlGaAs HBT HI/sub 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-b phase accumulator driving a vector modulator, implemented as a pair of balanced mixers, 5-b switched attenuators, buffer amplifiers, and central circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other products better than -50 dBc. Over a 32-dB control range, the 5-b switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50-250 MHz. DC-level variations versus attenuator-state limit the spurious response of an 800-MHz Composite DDS based on this serrodyne modulator to -20 dBc. Post-fabrication modeling indicates that a 5/spl deg/C thermal gradient across the IC may be responsible for this undesired dc-level variation. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz. >

Low power HFET down converter MMIC's for wireless communication applications

An ultra low power GaAs HFET (heterojunction FET) amplifier/mixer MMIC was designed and characterized for portable communication applications in the 900 MHz band. A completely monolithic LNA (80 mil/spl times/42 mil) achieved 10 dB gain, 2.5 dB NF and -4 dBm input IP3 at an operating current of 0.5 mA @ 1.0 V. Receiver sensitivity of a front-end circuit consisting of the LNA and a dual gate FET mixer was characterized using the 12 dB SINAD method. The IC achieved -117 dBm receiver sensitivity in the 900 MHz cellular band. The total power consumption of this miniature down converter was about 2 mW. The HFET down converter IC achieved the same receiver sensitivity as a MESFET down converter at 1/5th of the power. The extremely low power dissipation, high third order intercept point, high level of integration, and very good RF performance of this monolithic IC make it an ideal candidate for wireless applications.

Multiphase sinusoidal oscillator using the CFOA pole

A multiphase sinusoidal oscillator using the parasitic poles of current feedback operational amplifiers (CFOAs) is presented. The oscillator can generate n signals which are equal in amplitude and equally spaced in phase. The oscillator using the parasitic poles of CFOAs is suitable for high frequency applications and monolithic IC fabrication. The effects caused by the nonlinearity of the CFOA on the oscillation frequency and condition have been analysed. Experimental results show that a three-phase sinusoidal oscillator has a wide operating range from 10 kHz to 10 MHz and a large output voltage swing up to 7 V peak to peak while using +or-5 V power supply. The total harmonic distortion (THD) of each oscillation frequency is dominated by its third harmonic component which is at least 33 dB down from its fundamental.

Monolithic regulated self-biased HEMT MMIC's

This work benchmarks the first demonstration of a monolithic HEMT IC design which incorporates active regulated self-bias. The HEMT current regulator design consists of integrating an op-amp in a feedback configuration with the LNA to achieve gain, noise figure, and DC bias performance which is tolerant to threshold variations due to the HEMT process. The HEMT LNA bias current can be maintained to within /spl plusmn/3% variation over a process threshold variation (V,,) of /spl plusmn/0.5 V. The bias circuitry regulates the bias current to within 1.5% over a 100/spl deg/C temperature range. The amplifier has a nominal gain of 10 dB and a noise figure of 2.5 dB over a 1-10 GHz bandwidth. Across several wafers with a threshold voltage spread of 0.5 V, the regulated LNA maintains repeatable gain and noise figure which varies by less than 1 and 0.75 dB, respectively. The monolithic regulated self-bias technique can be integrated with other HEMT MMIC's in order to improve the performance and reliability, as well as to reduce the cost and weight of Integrated Microwave Assemblies (IMA's).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC

This paper describes the application of a monolithic Si bipolar IC to serve as a single-chip measurement instrument for pseudo-random binary sequence (PRBS) generation, bit error detection, de-scrambling, and trigger derivation up to 12.5 Gb/s. The package interconnect problem of high I/O count multi-Gb/s IC's is addressed. The paper presents a packaging solution with improved ground contact and odd-mode controlled impedance differential microstrip transmission lines. A method for phase synchronization of multiple PRBS generators is proposed and its feasibility is demonstrated by measurement results. >

A discrete phase-locked loop for undergraduate laboratories

Phase-locked loop (PLL) experiments in undergraduate instructional laboratories are usually designed around a monolithic IC chip. However, insight into circuit operation is mostly lost with use of the IC chip. In this paper, a PLL circuit consisting of only three transistors is presented. Given its simple topology, it can be realized with discrete components and requires minimal analysis. Hence, the presented circuit is ideally suited for demonstrating PLL principles in undergraduate laboratories.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Brief communication. Active-R realization of current-mode low-pass filters

An active-R realization of current-mode low-pass transfer functions is presented. Since the circuit is composed of only operational amplifiers and resistances, it is suitable for high frequency operation and monolithic IC implementation.

Synthesis of biquadratic filters from current conveyors

AbstractThis paper describes a circuit configuration for a biquad filter which utilizes the second‐generation current conveyors (CC II) and is capable of synthesizing an arbitrary second‐order transfer function.The circuit is composed of a subblock circuit with two positive CC IIs and a differential input circuit with two positive CC IIs.The subblock circuit realizes a lowpass, high‐pass, and bandpass filter. Combining this with the differential input circuit produces an all‐pass and notch filter.Each filter has a high input impedance because its input is the Y terminal of the CC II and can be cascaded without a buffer. The quality factor Q of the filter is determined by a ratio of passive elements, and its sensitivity to the passive element values is less than 0.5. These characteristics make the filters suitable for monolithic IC implementations. The effects of CC IIs voltage error ϵv and current error ϵi on the filter characteristics were studied. It was found that the center frequency ωo is independent of these errors, Q is affected only by ϵi, and the gain factor is a function of both ϵv and ϵi. Each filter was prototyped and was verified to operate as predicted.

Ion implanted material in highly integrated GaAs ICs

Selective ion implantation and epitaxy are beginning to increase the degree of integration of monolithic microwave ICs (MMICs). Most MMICs produced to date have only a single function per chip, for example the C‐band phased array radar T/R module illustrated in the Figure, but selective ion implantation has allowed a complex, multifunction GaAs MMIC to be realized recently. magnified image

A very small, low-loss MMIC rat-race hybrid using elevated coplanar waveguides

A very small, low-loss monolithic microwave IC (MMIC) rat-race hybrid using elevated coplanar waveguides is proposed. A 15-GHz-band rat-race hybrid was designed and fabricated in a 0.50 mm*0.55 mm chip area. The proposed hybrid requires less than half the area used when constructing miniaturized MMIC hybrids from thin-film microstrip lines. Furthermore, coupling loss of the proposed hybrid is reduced by approximately 2 dB in comparison to that of previously reported ones.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Small-signal MMIC amplifiers with bridged T-coil matching networks

Addresses the application of bridged T-coils to the design of multiplicative gain monolithic microwave IC (MMIC) amplifiers. The multiplicative gain MMIC amplifier exploits the broad-band matching properties of T-coils to achieve good input and output return loss, as well as high gain per stage. After reviewing the main theoretical aspects of this design approach, an actual circuit that provides gain, input, and output return losses in excess of 6, 10, and 8 dB, respectively, in the 50-MHz to 6-GHz bandwidth is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Physics-based electron device modelling and computer-aided MMIC design

On overview on the state of the art and future trends in physics-based electron device modelling for the computer-aided design of monolithic microwave ICs is provided. After a review of the main physics-based approaches to microwave modeling, special emphasis is placed on innovative developments relevant to circuit-oriented device performance assessment, such as efficient physics-based noise and parametric sensitivity analysis. The use of state-of-the-art physics-based analytical or numerical models for circuit analysis is discussed, with particular attention to the role of intermediate behavioral models in linking multidimensional device simulators with circuit analysis tools. Finally, the model requirements for yield-driven MMIC design are discussed, with the aim of pointing out the advantages of physics-based statistical device modeling; the possible use of computationally efficient approaches based on device sensitivity analysis for yield optimization is also considered. >

High speed class AB voltage-current convertor with improved accuracy

An improved class AB bipolar voltage-current convertor (VCCS) suitable for monolithic IC fabrication is described. Base-current compensation and bootstrapping are used to improve overall accuracy while preserving bandwidth and slewing rate. The conversion error is calculated and some experimental results are given which demonstrate the effectiveness of the proposed circuit configurations.

Au Wire Bonding to Cu Pad Using Ti Thin Film

An improved multilayer structure of a metal pad is developed for Au wire bonding to a monolithic IC. The proposed structure of the pad is Ti(2.5 nm)/Cu(800 nm)/Ti(70 nm)/Al(130 nm) on SiO2/Si substrates. Thermosonic Au wire bonding to the pad shows good bondability after heating at 473 K for the storage time of 3.6 ks in air. During heat treatment at 473 K after bonding, the bond between the Au wire and the pad is not degraded.

High-performance in W-band monolithic pseudomorphic InGaAs HEMT LNA's and design/analysis methodology

High-performance W-band monolithic one- and two-stage low noise amplifiers (LNAs) based on pseudomorphic InGaAs-GaAs HEMT devices have been developed. The one-stage amplifier has a measured noise figure of 5.1 dB with an associated gain of 7 dB from 92 to 95 GHz, and the two-stage amplifier has a measured small signal gain of 13.3 dB at 94 GHz and 17 dB at 89 GHz with a noise figure of 5.5 dB from 91 to 95 GHz. An eight-stage LNA built by cascading four of these monolithic two-stage LNA chips demonstrates 49 dB gain and 6.5 dB noise figure at 94 GHz. A rigorous analysis procedure was incorporated in the design, including accurate active device modeling and full-wave EM analysis of passive structures. The first pass success of these LNA chip designs indicates the importance of a rigorous design/analysis methodology in millimeter-wave monolithic IC development. >

Influence of Al Film Thickness on Bondability of Au Wire to Al Pad

In the Au wire bond to Al pad on a monolithic IC, it is found that the bond degradation due to heat treatment after thermosonic ball bonding depends on the thickness of the Al film on the SiO2/Si substrates. The bond degradation is lessened with thinning Al film. In the specimens with 0.2 μm and 0.5 μm Al films, the change in the bond resistance is small and the shear strength is almost invariable. In this case, the bond degradation is improved by reason of the fact that the volume of the diffused layer is reduced. It is also shown that the adhesion of the diffused layer to Au and SiO2 is very strong and a little Kirkendall void is detected. In the specimens with Al films thicker than 0.5 μm, the bond resistance much increases and the bond shear strength decreases.

Reduction of RMS jitter and phase deviation in 10 Gbit/s timing recovery circuit using monolithic ICs

A 10 Gbit/s timing recovery circuit using GaAs IC technologies is presented. A jitter suppression method using two cascaded differentiators is proposed. The phase deviation characteristics of a timing recovery circuit for mark density variation are also discussed.