Monolithic IC Research Articles

Tests and Analysis of Storage Life Extension of Hybrid Microcircuits for Aerospace Applications: A Case Study

Hybrid Microcircuits (HMCs) which bring about miniaturization with better performance and reliability are ideally suited for specific application where low volume requirement needed for aerospace missions. A large number of HMCs for varied applications are used in aerospace industry. HMCs generally use passive components and interconnections in thick film form, and active devices (MOSFETs, Transistor and Diode dice) and monolithic ICs (as bare chips) bonded to a substrate and are employed to carry out multiple functions. The die and other chip components utilized in making HMCs necessitated usage of hermetic sealing. The resulting HMCs consisting of multiple components are used as standalone EEE component. A general guideline of using HMCs for 9 years and re-screening after 3 years result in lot of constraint on resources and not viable in present scenario. The study conducted to find out the criticality and testing methodology for the extension of usable storage period. Comprehensive test plan consisting of variety of HMCs having varied processes, materials, density and various tests conducted as per the plan. This article details the various plans, choice of HMCs, testing results and analysis for the basis of extending the usable storage period of the HMCs for aerospace industry.

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

In this study, we present a low thermal budget elevated-laser-liquid-phase-epitaxy technique designed for the precise fabrication of single-crystal islands (SCIs) intended for use in middle-end-of-line (MEOL) FinFETs. Each of these SCIs features a (100) orientation tended from Si seeding structure and is successfully integrated as channel materials in the MEOL circuit of a monolithic 3D IC (3DIC). This technique effectively mitigates the typical performance disparities associated with poly-Si channel materials in upper tiers, addressing a significant challenge in advanced electronic device fabrication and potentially enhancing the performance and reliability of MEOL FinFETs in monolithic 3DIC.

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Enabling Co-Design of 3D Heterogeneous Packages

The days of ‘throwing it over the wall’ are over. Heterogeneous Integration (HI) is ushering in a new era of electronic product design with collaboration at its core – one that lives or dies on seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP) not only pushes the need for more advanced multi-die packaging, it makes packaging part and parcel of the process. And in doing so, it significantly reduces dependance on Moore’s Law at a time in which building an advanced monolithic system-on-chip (SoC) has become prohibitively expensive. For many tech companies, Moore’s Law no longer represents the best technical nor economical path to designing a product. And for a great many of those companies, HI presents a solution – SiPs close to the SoC form factor but with far lower overall cost, greater yield and perhaps most importantly, faster time to market. While SiP as a packaging concept has been around for decades, the recent tsunami of designs that have adopted HI is truly a disruptive change. This presentation will outline some potential solutions to the challenges design teams face when pivoting from monolithic IC design to 3D heterogenous package design.

Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations

Witnessing significant signs of a slowdown of Moore’s law and Dennard scaling has pushed leading semiconductor companies toward advanced packaging with heterogeneous integration (HI) to stay away from the challenges of monolithic IC in more shrunk technology with higher complexity. In light of the advances made in monolithic ICs, this paper explores how these promising solutions can be extended for secure HI. For this purpose, by investigating the trustworthiness of the system-in-package (SiP) supply chain, we introduce possible trust validation and attack mitigation methodologies leading to establishing the fundamentals of end-to-end secure HI.

An ILD Void Detection Method for Monolithic 3-D ICs Based on Switched Capacitors

Monolithic three-dimensional integrated circuits (M3D ICs) have a higher integration and better performance compared to 3D ICs based on through-silicon vias. However, high integration density and substantial scaling of the inter-layer dielectric (ILD) make M3D ICs extremely prone to occur process defects. In fact, defects such as voids often occur in the bonding process of M3D ICs. Therefore, ILD void detection is necessary in order to achieve high yield for M3D ICs. In this paper, an ILD void detection method based on switched capacitors is proposed. Since voids affect the equivalent capacitance of logic gates above the ILD, voids can be discovered by measuring the gate-level equivalent capacitance. And the value of the capacitance can reflect severity of the void. The effectiveness and accuracy of the proposed method are verified by HSpice simulations. For M3D ICs with the 22 nm process, the minimum capacitance variation identified by this method is 3.355 fF under process variation. And this means nanoscale voids can be detected by the proposed method.

Dice Selection in Hybrid Microcircuits For Aerospace Applications

Hybrid Microcircuits which bring about miniaturization with better performance and reliability are ideally suited for application specific low volume production requirement of space missions. A large number of HMCs are used in every spacecraft. HMCs generally use passive components and interconnections in thick film form, and active devices (MOSFETs, Transistor and Diode dice) and monolithic ICs (as bare chips) bonded to a substrate. Environmental radiation threat to ICs and other active circuitry is one of the major causes of failures in HMCs. The ionizing radiation present in the Van Allen Belt penetrates the satellite resulting in the excitation of electrons in the semiconductor valence band to conduction band in the active circuit and can be trapped. Secondary photon radiation, which are generated due to slowing down of high energy particles also strike interior of the spacecraft. The total interaction of various charged particles and photons to the internal circuitry of HMC depends on mass, charge state, kinetic energy of the striking photon as well as on the mass, charge and density of the die structure internal to HMC. The MOS die is prone to failure due to total ionization dose as well as single event effects which in turn may cause HMC failure. HMCs for space applications are mostly characterized with die passivation and hermetically sealed packages for its inherent advantages. In spite of the advantages offered by hermetic sealing like reliability, radiation shielding, out gassing etc, the radiation hardened dice are preferred for realization of HMCs for space systems. A feasibility study is carried out for using MIL and Commercial grade dice in HMCs without compromising on reliability aspects. The layout design, die attachment process, testing and extensive qualification become important in HMC apart from hermetic sealing so as to avoid catastrophic failure. This article details the radiation phenomena and its effects on dice used in HMCs. The advantages of hermetically sealed packages and use of MIL/Commercial grade dice in HMCs along with various mitigation techniques to have reliable circuit meeting the desired performance in space environment are also presented.

Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs

This paper proposes and demonstrates single-crystal Germanium (Ge) growth by elevated-laser-liquid-phase-epitaxy (ELLPE) and the fabrication of Ge Fin field-effect transistors (FinFETs) for the monolithic three-dimensional integrated circuits (monolithic 3D ICs). This technique permitted the fabrication of single-crystalline (100) Ge film and FinFETs without random grain boundaries. In comparison with the poly-Ge FinFETs, the ELLPE Ge FinFETs exhibit superior performance and uniformity. Moreover, the ANSYS simulated maximum temperature of bottom circuits during the ELLPE technique does not exceed 400°C, therefore allowing monolithic 3D integration of ICs.

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$157.48~\mu \text {m}^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.24~\mu \text {W}$ </tex-math></inline-formula> , respectively. The physical experiment of the proposed memristor emulator is performed using ALD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1106~n$ </tex-math></inline-formula> -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion

To unlock the full potential of monolithic gallium nitride (GaN) power integrated circuits, this article explores the feasibility of developing efficient and reliable on-chip gate driving and level shifting solutions, which fundamentally facilitate the on-chip implementation of GaN power circuits. As results, a self-bootstrapped hybrid (SBH) gate driving scheme and its circuitry are developed, which achieve rail-to-rail dynamic gate driving in normal operation and robust static gate driving in large transient moments. Meanwhile, an auto-lock auto-break (A2) level shifting technique is proposed to convert the gate driving control signals from low-voltage (LV) to high-voltage (HV) domains, without requiring any p-type devices. This enables the on-chip operation of high-side power switches and makes synchronous rectification possible. On-chip temperature sensing is implemented to monitor junction temperature directly at low circuit complexity and power and cost overheads, facilitating thermal protection at high power density. Furthermore, on-die dead-time control is presented to optimize zero voltage switching (ZVS) for high efficiency. All the techniques and circuits are demonstrated in a monolithic asymmetrical half-bridge (AHB) power converter on a GaN-on-SOI process. It achieves direct 48V/1V dc–dc conversion with a maximum load current of 5 A and a current density of 1.1 A/mm2. Among the existing monolithic GaN power ICs capable of on-chip synchronous rectification, it achieves the shortest rising- and falling-edge gate driving delays of 11.6 and 14.0 ns. Despite running doubled numbers of on-chip power transistors and gate drivers, it only consumes 70-mW static power.

VitRad: A low-cost continuous wave Doppler radar system with 3D-printed horn antennas for human vital sign detection

In this study, a low-cost continuous wave (CW) radar system with 3D-printed high-gain horn antennas called VitRad is proposed for human vital sign detection. The CW radar consists of 3D-printed high-gain horn antennas, commercially available low-cost surface-mounting devices, and monolithic ICs. The CW radar system operates at a frequency band of 5.8 GHz, and the backscattered I/Q data are collected using a digital storage oscilloscope (DSO). The data is processed on MATLAB to determine vital sign information such as respiratory and heartbeat rates. It is demonstrated that the proposed CW radar system for vital-sign monitoring can effectively measure respiratory and heartbeat rates.

Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs

Network-on-chips (NoCs) with traditional regular topologies generally have an average-hop-count increased, polynomially, with the network size. This brief proposes to generate brain-network-inspired (BNI) topologies on monolithic 3D (M3D) ICs, where the average hop count scales up logarithmically, for large-scale systems with tens of thousands of cores. We propose a routability-driven method to generate BNI topologies on M3D ICs with scale-free and small-world properties. Moreover, we present an iterative method to reduce the network diameter using as few tier-crossing routers as possible. The resulting BNI topologies not only have over 50% lower average hop count and lower diameter than traditional regular topologies, but also have shorter total link length than other irregular topologies. The performance is further validated by the cycle-accurate simulation.

Design and implementation of thermal collection networks in 3-D IC structures

The empirical affirmation in the electronics industry is that the power of chips per unit area is growing exponentially. The amount of heat generated is equal to the power; hence as power per unit area increases, so does the amount of heat generated within the chip. Thus, it necessary to mitigate the thermal problems of electronic systems. If not addressed or suppressed, thermal problems can lead to various issues including dielectric breakdown, electromigration, material creeping, unwanted chemical reactions, board warpage, drift in performance, and indirect heating. In this study, a dedicated thermal collection network (TCN) in the back end of the line area of an electronic chip was investigated. This network can help in creating a connection using a thermal through Silicon via (TTSV) to pump up the thermal energy to the heat-sink–fan assembly. Pre-empting heat from the sources could manage the thermal issues arising in chips as well as three-dimensional integrated circuit (3-D IC) structures. The finite-element method was the tool used for analysis. 31.62% of heat suction in TCNs of monolithic ICs, 11.36% in TCNs of 3-D IC structures, and 35.34% of heat suction in junctions of TTSVs compared with different approaches without the postulate used here. This procedure is expected to lead to a new path for redesigning electronic chips and 3-D IC structures.

A Novel Dual Output Comparator Based on Carbon Nanotube Field Effect Transistors Second Generation Current Controlled Conveyor

Background: Current comparators are useful in many analog circuits and communication systems. With the increasing demand to integrate wearable health monitoring systems in telemedicine and biomedical applications that help in early detection of abnormal conditions in patients, comparator is one of its cores. Objective: Wearable and implantable medical devices work primarily on the signal acquisition and wireless transmission. In the signal acquisition, Analog to Digital Converter (ADC) is the prime module. Conversion is done using the sampling process and samples are generated by comparing the input signal with the threshold level. For this purpose, comparator circuits are more preferable. This manuscript presents a novel dual output comparator design by using carbon nanotube field effect transistor second generation current controlled conveyor (CNCCCII). This CNCCCII is realized with the present- day technology called Carbon Nanotube Field Effect Transistors (CNFETs). Methods: The proposed comparator topology is designed with 32 nm CNFET technology files with a supply voltage of ±0.9 V using the Cadence Virtuoso simulator tool. The performance of the proposed design is tested using transient analysis, Montecarlo analysis, temperature sweep, and finally compared with the existing models. Results: The proposed comparator has the advantage of requiring a single CNCCCII with only one resistor and is preferable for monolithic IC fabrication. Conclusion: The proposed circuit implemented using CNFETs gives a substantial improvement in supply voltage requirement and less variation in output voltage levels over the existing technologies.

Design Automation and Test Solutions for Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

The approach of monolithic 3D IC (M3D) integration using monolithic inter-tier-vias (MIVs) as interconnect structures is considered. Although, M3D ICs show many benefits of heterogeneous integration without significant area overhead compared to 3D ICs, reliability and thermal issues become daunting challenges to be addressed. Hence, this study focuses on electromigration issues of current density, thermal stress, and structure deformation due to temperature loading. For the analysis Cu and carbon nanotube (CNT) filler materials were chosen in MIV structure. Our analysis reveals that CNT based MIV offers two-fold higher current density and 91% lesser thermal stress compared to Cu based MIVs. Furthermore, at different voltage values, the current density profiles are examined. For the comprehensive investigations of structure deformations, temperature gradient was allowed at the ends of the MIV structure. The results show less deformations in CNT compared to Cu, based on the stress induced among them. The failure time prediction shows higher mean time to failure value of CNT based MIV than Cu based MIV.

Effects of pre- and post-microwave annealing treatments on pGe MOS device

Effects of pre- and post- microwave annealing (MWA) treatment on electrical characteristics of p-type Ge substrate (pGe) metal-oxide-semiconductor (MOS) devices were investigated in this work. The physical mechanism was studied with an X-ray photoelectron spectroscopy analysis. The pre-MWA treatment, which is similar to conventional post oxidation annealing on interfacial layer (IL), can passivate the oxygen vacancy by chemisorbed oxygen. The excess chemisorbed oxygen atoms may be left at the interface between IL and high-k, which would induce more interface/oxide traps and form more unstable components in IL. The chemisorbed oxygen can be replaced with well-bonded oxygen by using a post-MWA treatment on high-k dielectric , instead of a conventional post deposition annealing. As a result, pGe MOS device with a double-MWA treatment exhibits low equivalent oxide thickness value (~0.65 nm), small frequency dispersion, low interface trap density, and excellent reliability characteristics without increasing the leakage current. The oxygen vacancy passivation and chemisorbed oxygen suppression with a double-MWA treatment are crucial for high performance Ge MOS device and monolithic 3D IC applications. • The effect of pre- and post- microwave annealing (MWA) treatment is compared. • Oxygen vacancy can be passivated by chemisorbed oxygen in pre MWA. • Excess chemisorbed oxygen can be replaced with well-bonded oxygen by post MWA. • A p-type Ge substrate capacitor can be improved by double MWA.

캔테나를 이용한 아두이노기반 FMCW 레이다 시스템 설계

In this study, the design of a low-cost frequency-modulated continuous wave (FMCW) radar system at C-band using commercial off-the-shelf (COTS) components is presented. The proposed radar system consists of low-cost surface-mounting devices and monolithic ICs on a multi-layer FR4 PCB for system integrity. The Tx/Rx antennas (Cantennas) were fabricated with commercial cans based on waveguide dominant mode analysis. The proposed radar system is connected to the Arduino UNO platform, which transfers the received analog backscattered RF signal to MATLAB to display a range versus time intensity (RTI) plot. The designed radar has a maximum detection range of 56.3 m.

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&amp;R Tool

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.