Molecular-pore-stacking Research Articles

Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes

Effects of post-etching treatment (PET) in trench patterning and resputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of molecular pore stacking (MPS). Optimized combination of PET and resputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times longer EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and resputtering, contributes to high reliability for 28nm node CMOS and beyond.

Effects of Postetching Treatment on Molecular-Pore-Stacking/Cu Interconnects for 28 nm Node and Beyond

The effects of postetching treatment (PET) using carbon-containing gas on molecular-pore-stacking (MPS)/Cu interconnects were investigated. By using this technology, a 5% reduction in wiring capacitance was obtained as a result of the hardening of exposed MPS at the trench bottom. Via-chain yield improvement was also confirmed as a result of eliminating of etching residues in via-holes. These results indicate that high production yield and reliability can be obtained by PET for 28-nm-node complementary metal oxide semiconductor (CMOS) devices and beyond.

Effects of Postetching Treatment on Molecular-Pore-Stacking/Cu Interconnects for 28 nm Node and Beyond

The effects of postetching treatment (PET) using carbon-containing gas on molecular-pore-stacking (MPS)/Cu interconnects were investigated. By using this technology, a 5% reduction in wiring capacitance was obtained as a result of the hardening of exposed MPS at the trench bottom. Via-chain yield improvement was also confirmed as a result of eliminating of etching residues in via-holes. These results indicate that high production yield and reliability can be obtained by PET for 28-nm-node complementary metal oxide semiconductor (CMOS) devices and beyond.

Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-k Films

Highly selective dry-etching processes are developed for conventional via-first (VF) pattering sequences to fabricate reliable Cu dual-damascene interconnects (DDI) in carbon-rich low-k films, such as a molecular-pore-stack (MPS) SiOCH film (k = 2.55). The carbon-rich MPS film, which had excellent endurance against plasma-processes, acted as etching stopper during hard-mask (HM)-etching on it, and the high selectivity of trench-HM etching reduced variability of over-etching depth in the MPS film. This effect reduced variability in trench-depth in the MPS film, or interconnect characteristics such as capacitance–resistance (C–R) time delay. The via yield and reliability were influenced also by via-etch selectivity of MPS against SiCN cap underlain. We found that the SiCN thickness remained after the via etch should be greater than 10 nm to prevent Cu from oxidation by O2 ashing step followed. Chemical-reaction-enhanced gas chemistry in N2–CFX–Ar system, i.e., high N2/Ar ratio under limited CFX supply, increased the etching selectivity of MPS to keep enough thickness of SiCN. Early-failure-mode in electro-migration test was suppressed by the high selective via-etch. Precise selectivity control for robust carbon-rich low-k films was very important to achieve the low variability and high reliability of scaled-down Cu interconnects.

Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects

A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film (k = 2.5) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles (θtop) were greater than 45° while keeping the bottom angle (θbtm) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with θbtm≪90°. Finite element method (FEM) simulation well explains the dependence of SiV reliability on both θtop and θbtm; the increment of θtop reduces the stress gradient under the via, while the decrease in θbtm enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance against the SiV due to relaxation of the stress gradient under the via.

Porous Low-k Impacts on Performance of Advanced LSI Devices with GHz Operations

The impact of porous low-k films on circuit performance in GHz operation was investigated using high-speed circuits in 65 nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore-stacking (MPS) SiOCH films, local low-k/Cu structures (M2–M5) with effective dielectric constants (Keff) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with Keff=3.4. The interline capacitance (Cint), measured using an LCR meter at ∼100 kHz, was reduced by 12% from Keff=3.4 to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ∼1.5 GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2 GHz static random access memory (SRAM) with Keff=2.9 provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in Vddmin, or eventually widening the SRAM operation margin. The porous low-k impact on GHz operation is demonstrated for the first time.

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Impact of barrier metal sputtering on physical and chemical damages in the low-k SiOCH films is investigated. In RF sputtering system, the potential drop across the anode sheath accelerates the ion in the plasma toward the wafer surface, inducing damages in the low-k SiOCH dielectrics. High DC bias on the target reduces the anode sheath voltage to suppress the process-induced damage in the SiOCH films. For conventional rigid and porous SiOCH films with methyl (–CH3) additives, the accelerated ions break the Si–CH3 bond, pushing up the dielectric constants. A new type of SiOCH film such as a molecular-pore-stacking (MPS) SiOCH, which is consisted of hexagonal silica ring with a large amount of hydrocarbon groups surrounding the core silica structure, exhibits high endurance to the sputtering-induced damages. The long side-chains of the hydrocarbon prevent the direct ion bonberdment to the core Si–CH3 bonds by sacrificing the C–C bond in the chains, keeping the low dielectric constant in the MPS SiOCH.

Molecular-level Manipulation Technology for Low-k Dielectrics Controlling the Physical and Chemical Structures toward 32nm-node BEOLs

ABSTRACTLow-k materials in advanced interconnect modules are required not only to lower the parasitic capacitances, but also to have mechanical stability with damage-less interfaces. By plasma-polymerization (PP) process using ring-type siloxane precursor, a new self-organized porous SiOCH film is developed with preserving the original hexagonal silica-backbone structure, thus so called as a molecular-pore-stack (MPS) SiOCH film. The hydrocarbon-rich MPS film has high endurance to the process damages. A density-modulated MPS film is obtained with reinforced interfaces by plasma co-polymerization (PcP) process using not only the ring-type but also linear-type siloxane. Furthermore, an ultimate full low-k module with low-k silica-amorphous-carbon composite (SACC) cap, instead of high-k SiCN, is also obtained simply by the one-step deposition scheme. The modulated PcP process and the sophisticated molecular design of the precursor siloxane provides scaled-down interconnect modules with good mechanical strength and excellent dielectric reliability at a low manufacturing cost, applicable for 45/32/22nm-nodes ULSIs.

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations