Abstract
Effects of post-etching treatment (PET) in trench patterning and resputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of molecular pore stacking (MPS). Optimized combination of PET and resputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times longer EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and resputtering, contributes to high reliability for 28nm node CMOS and beyond.
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