Abstract
Effects of post-etching treatment (PET) in trench patterning and re-sputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of Molecular Pore Stacking (MPS). Optimized combination of PET and re-sputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times loger EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and re-sputtering, contributes to highly reliability for 28 nm node CMOS and beyond.
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