Modular Redundant System Research Articles

The design of totally self-checking TMR fault-tolerant systems

A totally self-checking triple modular redundancy (TSC-TMR) system consists of a conventional TMR system monitored by a TSC circuit with two outputs indicating information errors and internal faults. The internal fault indication is independent of the output information errors and indicates masked errors of modular units or faults in the monitoring circuit itself. The information error indication depends mainly on the output information errors and it can be used as a stop signal preventing the propagation of erroneous outputs. This scheme of fault-tolerant systems is very simple and reliable compared to the known TMR systems with self-checking capabilities and achieves a high degree of availability and maintainability. The TSC error checking circuit has been designed by applying a new algebraic technique with two basic operator blocks performing the AND and XOR operations on error indication variables. >

Dual Versus Triplication Reliability Estimations

The system mean time to failure (MTTF), a measure of reliability, depends largely on the failure rate, the mean time to repair, and the coverage factor. All contribute to the calculation of MTTF and influence the system design in terms of reliability objectives. In dynamically redundant systems, such as dual systems, coverage plays an extremely important role. It is a probability that the system will recover from a single fault. This involves both hardware and software components to properly detect, isolate, and reconfigure around a faulty module without adversely affecting the system operation. A small reduction in coverage can affect the MTTF dramatically. In a static redundant triple modular redundancy (TMR) system, the inherent error detection and correction property gives a near-perfect coverage for the first detected fault. As a result, the calculated MTTF of a TMR configuration is substantially greater than that of a dual system. This paper discusses and compares the reliability estimation of dual and TMR systems.

The Effect of Incomplete and Deleterious Periodic Maintenance on Fault-Tolerant Computer Systems

Maintenance is a common technique to achieve the reliability requirements of fault-tolerant computer systems. Depending on the system, maintenance may be carried out upon the failure of any one module, at regular intervals, or subject to some other maintenance strategy. Due to human factors, maintenance is not always perfect, contrary to usual assumptions. There are several classes of imperfection that adequately describe maintenance strategies. A system with scheduled shut-down times for maintenance is best described by maintenance action that might be incomplete. On the other hand, a system which has to be diagnosed or maintained on-line is best described by maintenance action that may provoke a system failure; we term this deleterious maintenance. This paper examines these two classes of imperfection and obtains mean time-to-first-failure for each class. The results of three studies on Triple Modular Redundancy (TMR) systems are given for the case of maintenance induced failures in fault-tolerant computer systems. In systems with maintenance-induced failure, an optimum maintenance interval exists. The optimum MTFF is less than the optimum MTFF obtained if perfect maintenance is assumed. This is the limit to which maintenance can be used to improve the performance of the system. To increase MTFF beyond this, spares must be used. When these spares are substituted, the probability of inducing a failure must be much lower than that of maintenance-induced failure. For systems which have to be maintained on-line, it is important not to neglect the case of deleterious maintenance.

Further Comments on "The Reliability of Periodically Repaired n –l/n Parallel Redundant Systems"

In the original correspondence,1 Cantarella assumed a system consisting ot n parallel identical elements, each with a constant failure rate A. The system is repaired every T hours. An approximation n(n -1) A2T/2 for the average failure rate was derived. In further correspondence, 2 Nilsson derived an exact ciosed form expression for the failure rate. In this comment, we correct an algebraic error in Nilsson's approximation for small values of A. T, and also point out the relevance of both correspondences to the case where n is small, as in a triple modular redundant (TMR) system.

Diagnosability for fault tolerant parallel systems

In this paper a new approach to t-fault-diagnosability is presented. This is applied to a new parallel system, referred to as SADD, System Architecture for Distributed Diagnosability. SADD uses t-fault-diagnosis to attain high throuput without a reduction in fault tolerance as compared to modular redundancy systems. The system is divided into stations to facilitate the distributed diagnosability. The diagnosis procedure consists of a fault identification phase (prior to system testing) and a Byzantine General's Algorithm. The conditions of fault identification and diagnosability are presented. No central controller is required, and a remarkable improvement is achieved compared with existing systems (an almost 100% improvement), which use t-diagnosis.

Interrupt handling in the loosely synchronized TMR system

AbstractThis paper discusses problems in the implementation of interrupt handling in the loosely synchronized Triple Modular Redundancy (TMR) system where synchronization, majority‐decision and fault diagnosis are performed by software. The method of solution for the problems also is discussed. The major problems are as follows: (1) For the interrupt coming into three processors with a certain time difference in the task progress, the consistency among the global areas of the processors must be maintained; (2) The synchronization must be maintained among processors, which do not recognize interrupts due to the interrupt‐inhibit period containing synchronization, and the processors, which recognized the interrupts; (3) When interrupts at different levels arrive at a processor, each processor must identify the interrupt with the highest priority consistently. To solve these problems, we have developed a multitask scheduler, which provides the variable representing the number of access to the global area, the flag indicating the interrupt‐inhibit area, and the variable keeping the record of the accepted levels. This scheduler also controls the interrupt process by mutually referring those variables and flags. The system is implemented in SAFE system, and the overhead in the interrupt handling was measured.

Analysis of series deviance in a parallel state transition diagram and applications to fault tolerant computing

In this paper the effect of deviance on a parallel state transition diagram is analyzed. The attributes of deviance are identified by a modification in the system characterization which resembles the effects of fault/failure on a fault tolerant system operation. The steady state availabilities of two deviances are determined and the applicability of these results to static and dynamic N Modular Redundancy Systems, is presented.

Reliability study of duplex-hybrid systems

Duplex (double modular redundant) systems utilising standby spares are described and the reliability equations of such systems are derived. The system reliability as a function of normalised time is plotted and compared with conventional TMR (triple modular redundant) system. It is shown that the duplex-hybrid system is noticeably more reliable than the TMR-hybrid system with the similar configuration of standby spares. Implementation of a duplex-hybrid system supplemented by an intelligent unit with powerful capabilities is discussed.

Reliability evaluation of a TMR computer system with multivariate exponential failures and a general repair

A Triple Modular Redundant (TMR) computer system is discussed under the assumptions of the multivariate exponential lifetimes and a general repair distribution. Analysis of an extended Markov Renewal Process (MRP) enables us to formulate a stochastic model and give some reliability measures which are quite useful to evaluate the TMR computer system.

Reliability Analysis and Optimal Redundancy for Majority-Voted Logic Circuits

A scheme using multiple redundant computing devices with a majority voter improves the reliability of the output of the computing device. This paper analyzes some modular redundant systems with majority voters. An iterative structure is introduced for voters in order to improve the total reliability. The reliability of voters is introduced in several ways. Two models of imperfect voters are discussed in detail, that is, output-imperfect model and semiperfect model. The former is suitable for the case where voters are treated in the same manner as other modules. The latter is appropriate for the case where the characteristics of the voter are taken into account. Three theorems show the existence of optimal majority-voted logic circuit for a given value of the reliability of each module under some reasonable assumptions.

Correction to ``Reliability Modeling and Analysis of General Modular Redundant Systems''

Correction to ``Reliability Modeling and Analysis of General Modular Redundant Systems''

A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures

This paper deals with a method for designing a digital system which will remain operational in spite of the failure of some of its components. A scheme and its realization are presented for automatically reconfiguring a 5MR (five modular redundancy system or 5-input majority voting system) into a triple modular redundancy (TMR) system under a single or double module failures. The scheme can tolerate a double fault followed by a single fault which can neither be tolerated by a 5MR nor by a hybrid redundancy system with a TMR core. It uses no spare units and the circuit realization is relatively simple. The modular structure of the logic design for the proposed scheme should make the testing of the system easier. The scheme can be used in both binary and multivalued systems.

Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults

It is well known that static redundancy techniques are very efficient against intermittent (transient) faults which constitute a large portion of logic faults in digital systems. However, very little theoretical work has been done in evaluating the reliability of modular redundancy systems which are subject to intermittent malfunction occurrences. In this paper we present a statistical model for intermittent faults and use it to analyze the reliability of NMR systems in mixed intermittent and permanent fault environments.

A new approach to reliability optimization in general modular redundant systems : Krishna Gopal, K. K. Aggarwal and J. S. Gupta. Microelectron. Reliab.18, 419 (1978)

A new approach to reliability optimization in general modular redundant systems : Krishna Gopal, K. K. Aggarwal and J. S. Gupta. Microelectron. Reliab.18, 419 (1978)

A new approach to reliability optimization in general modular redundant systems

The paper proposes a new technique for solution of reliability optimization problem in modular redundant systems whose sybsystems may be in series or complex configuration and are subject to multiple linear and/or nonlinear constraints. Modules within a subsystem may be statistically dependent or independent. In each subsystem redundant modules can be added in any one of the redundant modes (active parallel, standby or partial ( k-out-of- n: G) redundant mode) or a more reliable module can be used in order to improve the system reliability. The gain in system reliability by allocating all the available resources to one subsystem only are determined for all subsystems and to the subsystem giving the maximum gain one redundant module is added or a more reliable module is used in that subsystem. The method has been illustrated by examples and results compared with existing methods.

Reliability modeling and analysis of general modular redundant systems : Francis P. Mathur and Paulo T. de Sousa. IEEE Trans. Reliab.R-24, (5) 296 (Dec. 1975)

Reliability modeling and analysis of general modular redundant systems : Francis P. Mathur and Paulo T. de Sousa. IEEE Trans. Reliab.R-24, (5) 296 (Dec. 1975)

Reliability Modeling and Analysis of General Modular Redundant Systems

Hardware redundancy has been used in the design of fault-tolerant digital systems. A synthesis of protective hardware redundancy techniques is proposed and a generalized reliability model suitable for many fault-tolerant configurations is developed. This model, to be called General Modular Redundancy (GMR), yields as particular cases several known models of redundant structures.

A Reliability and Comparative Analysis of Two Standby System Configurations

Equations are derived which enable one to calculate the system reliability for parallel or triple modular redundant systems with standby spares. Software error detection is introduced into the TMR/Spares system configuration in order to utilize fully all of the units. An indication of the sensitivity of the system reliability to an increase in the number of spares, partitioning, switching, variations in the powered and unpowered failures rates, and time is presented. A comparison of the parallel and the TMR/Spares system configurations, under similar conditions, is given.