This article presents a new systematic technique for identifying voltage traveling waves (TWs) to determine the location of line faults in half-bridge modular multilevel converter-based high-voltage dc (HBMMC-HVdc) grids. In this technique, the buffered voltage signal frame around the fault-detection time is first scaled and then segmented via an optimization process. Finally, the incident/reflected TWs arrival times are obtained by executing a simple search algorithm on the reconstructed signal segments’ differences. This article describes how to use this technique in three forms of TW-based fault location schemes, including the single-ended scheme with known TW velocity, the double-ended scheme with known TW velocity, and the double-ended scheme with unknown TW velocity. The application results on a four-terminal HBMMC-HVdc grid simulated with exact component models show the proposed technique’s high capability and accuracy in all the three TW-based fault-location schemes. According to these results, the average fault-location errors are less than 0.5% for all the schemes. The numerical results also confirm that the proposed technique maintains its excellent performance, even in the face of close to terminal faults with distances down to 4 km, faults with high resistances up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$450 \Omega $ </tex-math></inline-formula> , and noisy signals with signal-to-noise ratios down to 55 dB. Moreover, the comparison results confirm that the proposed approach is more tolerant of measurement noise than the wavelet transform.