Modified Variable Threshold Logic Research Articles

High-speed decimation filter for delta-sigma analog-to-digital converter

A 12-bit digital filter is designed for an A/D converter system with sampling speed of 16 GHz. Data stream of 16 Gbit/s from delta-sigma modulator will pass through a 1:4 demultiplexer. Four identical 12-bit digital filters are used to catch the data streams from the demultiplexer for 4 Gbit/s in each channel. The 12-bit superconductive digital filter is designed with modified variable threshold logic (MVTL) gates. A novel XOR gate is designed and used in this circuit to reduce circuit complexity and improve performance. Progress of high speed testing results is presented. The filter comprises 584 Josephson junctions and consumes about 1 mW power.

Monte Carlo optimization of superconducting complementary output switching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.

Decimation filter with novel MVTL XOR gate

A single-rail Modified Variable Threshold Logic (MVTL) decimation filter is designed by employing a novel XOR gate, which overcomes the difficulty of the lack of a good inverter in the MVTL logic family. A 10-bit deep-pipelined decimation filter consisting of about 700 junctions in a 5 mm/spl times/5 mm chip with power consumption of 0.4 mW is designed.

Interface circuits for chip-to-chip data transfer at GHz rates

Interface circuits for the transfer of data between Single Flux Quantum (SPQ) circuits have been designed, fabricated, and operated at speeds up to 3 Gigabits per second. The circuit employed an improved version of the SFQ/Latch converter, a Modified Variable Threshold Logic (MVTL) OR/AND gate, a 3/spl times/ latching amplifier, and a 3/spl times/-to-10/spl times/ latching amplifier. The amplifier circuits employed stacks of latching junctions. Resistors between the parallel stacks of junctions damped residual currents to prevent flux trapping during reset. Tolerance to critical current variations in the series stacks of junctions was provided by inductive chokes on the input junction shunting resistors. Microwave modeling programs were used to ensure proper distribution of the applied current to all of the latching elements. The circuit transferred data at 3 Gigabits per second from one SFQ circuit up to room temperature and back to another SFQ circuit through 3.4 meters of 50-ohm cable.

FD-TLM electromagnetic field simulation of high-speed Josephson junction digital logic gates

The finite-difference transmission line matrix (FD-TLM) method is extended to modeling low-T/sub c/ Josephson junction (JJ) digital logic integrated circuits (IC's), providing comprehensive simultaneous time-domain, three-dimensional (3-D) full-wave electromagnetic field and JJ device analysis. Techniques for FD-TLM modeling of a Josephson Atto-Webber switch (JAWS), a two-junction superconducting quantum interference device (SQUID), and modified variable threshold logic (MVTL) logic gates are discussed and simulation results are presented. Interconnection lengths are intentionally short so that the full-wave FD-TLM simulation results can be validated with results of conventional quasistatic-based circuit simulations. Good agreement between the simulation techniques validates the FD-TLM JJ logic circuit modeling approach. In the FD-TLM method the electromagnetic behavior of the circuit is modeled from the material properties and dimensions of the circuit, avoiding separate extractions of parasitic capacitance and inductance as needed in conventional circuit simulations.

Complementary output switching logic-a new superconducting voltage-state logic family

A new superconducting logic family, complementary output switching logic (COSL), is proposed. The family consists of AND, NAND, OR, NOR, and XOR gates. The performance of the gates is predicted with a procedure that evaluates the dynamic performance when all circuit parameters are randomly varied around the nominal values. The simulated performance of the gates is compared with modified variable threshold logic (MVTL) at 5 GHz and 10 GHz. The functionality and margins of the COSL gates are verified by measurements at low speed.

Niobium based Josephson circuit technology

Abstract Since the introduction of reliable niobium junctions, Josephson circuit technology has made remarkable progress. We have demonstrated high speed Josephson circuits such as a 4-bit microprocessor and an 8-bit digital signal processor. In this paper, we describe key technologies to realize these circuits, mainly from the viewpoint of circuit design. One of them is the high speed modified variable threshold logic (MVTL) gates which have a large operating margin and high sensitivity. Another is the three-phase ac power system. This power method requires no latching circuits, making the circuitry very simple and resulting in high speed operation. For designing large scale circuits, a systematic design method is also important. Josephson logic has latching characteristics and requires alternate current supply that is quite different from semiconductor logic. We modified existing tools for semiconductor circuits and established a new design system. We also introduced scan path registers for testing the circuit. Using two scan path registers, one at the input and one at the output, we demonstrated RAM read out operation.

Bit-serial multiplier based on Josephson latching logic

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Performance of MVTL OR-AND gates when data precedes bias

A six-stage shift register based on modified-variable-threshold-logic (MVTL) OR-AND gates using 90 Nb/Al-Al/sub 2/O/sub 3//Nb Josephson junctions has been fabricated and tested up to 3.0 GHz. Bias current margins of the shift register were measured to be +or-26% at 200 MHz and below, +or-11% at 2.2 GHz, and +or-1.2% at 3.0 GHz. Calculation of the lobe plots for the OR gate shows that the expected margin is +or-26% when the control current (data) precedes the bias current (clock), and when no appreciable control current is injected into the superconducting quantum interference device (SQUID) loop via the injector junction. Special taps were included in the circuit so that the switching action of each of the 18 gates could be monitored in detail without disturbing the high-speed operation of the circuit. >

Josephson macrocell array

A modified variable-threshold logic (MVTL) gate for use in Josephson LSI circuits is considered. A 7.6 K-gate Josephison macrocell array whose functions can be changed by wiring changing has been developed. Automatic design problems, such as AC powering and small fan-outs, are solved by constructing the macrocell with a three-phase powering system and developing a magnetically coupled unit cell. The chip contains 21440 Josephson junctions on a 5 mm*5 mm die and is fabricated using 1.5 mu m all-niobium Josephson techniques. An average delay of 5.3 ps/gate in the macrocell and a total chip power consumption of 23 mW have been obtained. >

High-speed Josephson processor technology

High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.

Recent advances in Josephson junction devices

The paper describes recent advances in high-speed digital circuits using all niobium (Nb/AlO x/Nb) Josephson junctions. The world's fastest logic gate modified variable threshold logic (MVTL) is described. The MVTL gate family has been applied to various logic circuits such as a 16-bit ALU and a 4-bit microprocessor. The high-speed performance of Josephson junctions in LSI-level circuits has been verified using these circuits.

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 mu W/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Josephson modified variable threshold logic gates for use in ultra-high-speed LSI

A gate family called modified variable threshold logic (MVTL) is proposed. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, an operating margin of +or-43% and a switching speed of 2.5 ps/gate are obtained. the gate area is 30 mu m*24 mu m with a 1.5- mu m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit*16-bit multiplier, and a 16-bit arithmetic logic unit have been successfully operated. When the Josephson gate is operated with three-phase power, it is possible to construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Josephson pseudorandom bit-sequence generator

A nine-bit Josephson pseudorandom bit-sequence generator for use in Josephson computers and signal processors is described. The gates used in the circuit are modified variable threshold logic (MVTL) gates fabricated using 2.5- mu m Nb-AlO/sub x/-Nb junction technology with Mo resistors and SiO/sub 2/ insulation. They are driven by a three-phase power supply. The circuit consists of 66 gates and its area is 4.2*0.5 mm/sup 2/. Correct bit sequences with one period of 2/sup 9/-1=511 clocks were obtained. Its power consumption was 0.9 mW. The circuit operated at a clock frequency of up to 2.2 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Josephson 8-bit shift register

A Josephson 8-bit shift register for use in Josephson computers and signal processors is described. The gates used in the circuit are modified variable threshold logic (MVTL) gates fabricated by 2.5-/spl mu/m Nb/AlO/SUB x//Nb junction technology with Mo resistors and SiO/SUB 2/ insulation. They are driven by a three-phase power supply. The shift register has 112 gates and occupies a 1.1/spl times/2.1-mm/SUP 2/ area. Correct shift, load, hold, and clear operations were experimentally confirmed for all bits. The circuit operated at a clock frequency up to 2.3 GHz. Its power consumption was 1.8 mW. This power level is two or three orders of magnitude lower than for Si or GaAs shift registers.

High-speed unit-cell for Josephson LSI circuits using Nb/AlO&amp;lt;inf&amp;gt;x&amp;lt;/inf&amp;gt;/Nb junctions

In this paper, we will discuss the design, fabrication and evaluation of an OR gate and a unit-cell for Josephson logic LSI circuits using all niobium junctions. We fabricated the unit-cell using two Modified Variable Threshold Logic (MVTL) OR gates and one single-junction AND gate. The cell performs the logical opration (A+B).(C+D), which is the basic operation of the dual rail logic method, suitable for Josephson devices. The gates utilized Nb/AlO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /Nb Josephson junctions with a minimum diameter of 2.5 μm, Nb wirings, Mo resistors, and SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulators. The cell size, complete with supply resistors, was 82 μm × 132 μm. The gate delays were measured using the Josephson sampling technique with two sampling heads. The minimum delay of the OR gate in the cell was 4.2 ps, and that of the three-fanout cell was 11.5 ps. The experimental results were consistent with calculations based on measured parameters.

Feasibility of an ultra-high-speed Josephson multiplier

The authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all-niobium junctions. They designed a 16-bit /spl times/ 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) OR-gates and single-junction AND gates. These gates consisted of Nb/AlO/SUB x//Nb Josephson junctions, Nb wiring, Mo resistors, and SiO/SUB 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 /spl mu/m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wiring was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra high-speed multiplier, about five times faster than any semiconductor device.

Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctions

The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlO x /Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.