Abstract
The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlO x /Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.
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