Modified Derivative Superposition Research Articles

A two stage cascode LNA using modified derivative superposition technique in [formula omitted] HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard

A two stage cascode Low Noise Amplifier (LNA) is designed in 130 nm SiGe HBT. The work focuses on achieving a low Noise Figure (NF), high linearity, and high gain for the LNA in the frequency band of 57.24 GHz-65.88 GHz to be operated in all the four channels of IEEE 802.11ad standard. A modified Derivative SuperPosition technique is used in the first stage of the cascaded LNA to improve the linearity of the circuit. Post layout Electromagnetic (EM) simulation results of the proposed LNA achieves a peak gain of 20.19dB at 59.5GHz, linearity (IIP3) of 2dBm at the maximum gain and also achieved a NF of 4.1dB - 4.8dB in the operating band of frequency. DC power consumption of the proposed circuit is 9.2mW from a supply voltage of 1.2V, with an area occupancy of 311μm×298μm.

A 0.65 V, linearized cascade UWB LNA by application of modified derivative superposition technique in 130 nm CMOS technology

In this paper, a low-voltage linearized ultra-wideband (UWB) low noise amplifier (LNA) is presented. The core of the proposed circuit is a two-stage cascade structure which is forward body biased to operate under a low supply voltage. In the proposed topology the low linearity drawback of the cascade structure is improved by exploiting the modified derivative superposition (MDS) technique at the second stage. The MDS technique consists of an auxiliary transistor biased in the moderate inversion region paralleled with the main transistor biased in the strong inversion region and two degeneration inductors connected at the source node of the main and auxiliary transistors which altogether aim to cancel out contributions of both the second and third-order non-linearity coefficients on the third-order input intercept point (IIP3). Applying MDS technique on cascade structure has the advantage to have both high linearity and low supply voltage features in an UWB LNA. Simulated at post-layout level in 130 nm RFCMOS TSMC technology, the structure features a 13.8 dBm IIP3, consuming only 11.2 mW from a low supply voltage of 0.65 V. The proposed LNA achieves a relatively flat gain of 12 ± 1 dB, noise figure of 1.8–4 dB, and return power loss less than − 10 dB.

A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

A wide band resistive feedback CMOS low noise amplifier (LNA) with Modified Derivative Superposition (MDS) technique is designed by using TSMC RF CMOS 0.18μm technology. In this paper, the main NMOS transistor is biased in strong inversion and auxiliary NMOS transistor is biased in the moderate inversion, so third order nonlinear current of two transistors can be canceled out and high third order input intercept point (IIP3) can be attained. In other method, the main NMOS transistor is biased in moderate inversion and an auxiliary PMOS transistor is biased in weak inversion. By this technique, second and third order input intercept point (IIP2 and IIP3) are improved. With common gate transistor in cascode structure and auxiliary transistor, thermal noise of main transistor can be canceled. The linearized LNA demonstrates IIP2 and IIP3 average improvement of +17dB and +18dB with PMOS transistor rather than NMOS transistor in the frequency range of 3.1–10.6GHz. Maximum power gain of 22dB, minimum noise figure (NF) of 2.3dB with a power dissipation of 5.3mW (without buffer) are obtained under a 1.8V power supply in the frequency range of 5–10.6GHz. The chip area is 660µm×748µm.

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

Folded Cascode (FC) Low Noise Amplifier (LNA) is preferred for low voltage and low power RF applications. A FC LNA with gm-boosting technique is reported in the literature. Under low voltage operation, linearity of the LNAs is degraded due to transconductance and drain conductance nonlinearities. To improve the linearity of the LNAs, several techniques namely Harmonic Termination Network, Derivative Superposition, Modified Derivative Superposition (MDS) techniques are reported in the literature. In this paper to achieve high linearity for the gm-boosting FC LNA, MDS technique is incorporated at the Common Source (CS) stage and is proposed. In order to evaluate the efficacy of this approach, the proposed LNA is designed and implemented in UMC 0.18µm MMRF CMOS process for 2.44GHz. From the simulation results, it is found that the proposed LNA achieves a gain (S21) of 14.6dB, Noise Figure (NF) of 2.9dB, Input matching (S11) of −15dB and third order Input Intercept Point (IIP3) of +4.19dBm. The power consumption of LNA is 3.8mW for a supply voltage of 0.6V. The proposed LNA has a higher Figure of Merit (FoM) than that of other Cascode LNAs reported in the literature.

A high gain and high linearity current‐reused CMOS LNA using modified derivative superposition technique with bulk‐bias control

ABSTRACTThis article presents the design of a 2.4 GHz low power high gain and high linearity current‐reused CMOS low noise amplifier (LNA) using modified derivative superposition (MDS) technique with bulk‐bias control. The MDS technique with bulk‐bias control is used to extend the auxiliary transistor's bias control range and enhance the linearity performance. The current‐reused topology is utilized to fulfill the low power consumption and high gain, simultaneously. The proposed LNA is fabricated in a 0.18‐μm 1P6M SiGe BiCMOS process and consumes a 6.53 mA quiescent current from a 1 V voltage supply. The measurement results show that the proposed LNA achieves a 24.1 dB power gain, 1.7 dB NF, −18 dB input P1dB, 8.75 dBm IIP3, 13.9 and 19.5 dB input and output return loss, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2444–2446, 2014

A highly linear squarer design for energy-detection RF receivers

A highly linear Gilbert cell squarer is designed using a modified derivative superposition (MDS) technique, which employs a pair of NMOS–PMOS auxiliary transistors in weak inversion and an auxiliary PMOS transistor in moderate inversion. This technique reduces the inherent sensitivity of derivative superposition linearization schemes to bias voltage level. The Volterra series analysis of the squarer is reported to examine the effectiveness of the new technique. Simulation result using TSMC 0.13μm CMOS technology, demonstrates that MDS gives rise to 15dB improvement in IIP2 and 5dB improvement in IIP3 of squarer. Moreover, Bias voltage of squarer can be tolerated within 0.45–0.6V with acceptable IIP2 and IIP3 performances. The new linearization technique is applicable to RF modules in many wireless communications.

A High linearity CMOS low noise amplifier for 3.66 GHz applications using current-reused topology

A narrow band CMOS low noise amplifier (LNA) achieving high third-order input intercept point (IIP3) is proposed exploiting a non-linearity cancelation technique at RF frequency. In the modified derivative superposition (MDS) technique, one transistor is biased in the strong inversion region and the other is biased in the moderate inversion region instead of weak inversion region. A current-reused technique is employed to increase the trans-conductance (gm) of the amplifier and as well as the gain of LNA without increasing the power consumption. The linear LNA was designed and simulated in 0.13μm CMOS process. A gain of 14dB at 3.66GHz was exhibited and the simulated noise figure (NF) was 2dB. An IIP3 of 10.5dBm and a power consumption of 2.4mW from a 0.8V supply voltage were achieved. An input return loss (S11) of −10.6dB and an output return loss (S22) of −27dB were provided.