Modified Booth Encoding Research Articles

A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique

High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved. A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, when two numbers are multiplied some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose Spurious Power Suppression Technique (SPST) is used to remove useless portion of the data in addition process. In this modified architecture, the overall process is three stages to produce the result. The modified MAC operation is coded with Verilog and simulated using Xilinx 12.1.

A Low-Power Hybrid Multiplication Technique for Higher Radix Hard Multiples Suppression

This paper presents a low-power higher radix multiplication algorithm based on Radix-16 32×32 bit Modified Booth Encoder (MBE). Hard multiples are the major factors for power consumption in higher radix MBE. This paper introduces the design of a Hybrid Multiplication Technique (HMT) to suppress the hard multiples that exist in a Radix-16 32×32 bit MBE. The proposed HMT uses Radix-8 and Radix-4 encoding technique along with Radix-16 to avoid the hard multiples. Experimental results based on Synopsys SDK 90nm, 1.32V standard-cell library show that the proposed HMT reduces power consumption up to 25% and 21% in comparison with conventional Radix-16 and Radix-8 MBE respectively. HMT equipped Radix-16 MBE also gives better performance than existing techniques with respect to frequency and power.

IJARCCE - Computer and Communication Engineering

2 Abstract: A new architecture namely 2-D DWT, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. the simulation is done on the Modelsim and finally output is analysed by using Matlab.

An Design of Radix-4 Modified Booth Encoded Multiplier and Optimised Carry Select Adder Design for Efficient Area and Delay

An Design of Radix-4 Modified Booth Encoded Multiplier and Optimised Carry Select Adder Design for Efficient Area and Delay

IJIREEICE - Electrical, Electronics, Instrumentation and Control

A new architecture, namely, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx FPGA device. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product.

Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier

In this paper, we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial product array (PPA) of existing PEB multiplier uses partial product bit as guard bit for sign extension. This is not an efficient approach as extra half-adders (HAs) are required to accumulate these sign extension bits. We have considered PPA of conventional modified Booth encoded (MBE) multiplier where logic `1' is used as guard bit for sign extension. Logic `1' in the PPA helps to replace HA with a NOT-gate in the adder design. Based on the proposed scheme, we have derived an efficient adder design for PEB radix-4 Booth multiplier. Compared with the adder design of existing PEB multiplier, the proposed adder involves less logic resources and less critical path delay (CPD), and calculates the same compensation value. ASIC synthesis result shows that the proposed PEB radix-4 Booth multiplier of sizes n = 8, 10, 12, and 16, respectively, involves 18, 19, 16, and 13 % less area-delay product (ADP), and 12, 16, 11, and 12 % less power consumption than the existing PEB multiplier. We have shown that an inner-product (IP) cell based on proposed fixed-width radix-4 Booth multiplier involves 11.3 % less ADP and consumes nearly 7.6 % less power than an IP cell based on the existing PEB-based fixed-width multiplier on average for different inner-product sizes. The proposed multiplier is, therefore, a useful component to develop high-performance systems for digital signal processing applications.

Implementation of Modified Booth Encoding Multiplier for signed and unsigned 32 bit numbers

This paper presents the design and implementation of Modified Booth encoding multiplier for both signed and unsigned 32 - bit numbers multiplication. The already existed Modified Booth Encoding multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Whereas the array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requirement of the modern computer system is a dedicated and very high speed unique multiplier unit for signed and unsigned numbers. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Index Terms: Modified Booth Encoding multiplier, Baugh-Wooley multiplier, array multiplier, CSA, CLA Partial product, Signed-unsigned.

A noval Approch of area efficient and fast radix 2^3 means (8) modified booth multiplier

Array multiplier occupies larger area so MBE is engaging approach to style efficient multiplier. This paper presents new concept which is able to optimize the realm and speed of information calculation. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign little bit of the operands and generating an extra partial product the SUMBE multiplier obtained. Parallel Prefix Adder wont to speed up the number operation. The new approach of 2’S complement has been introduced during this paper to cut back the realm of MBE.

Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding

In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for both operands in the weighted representation is proposed. Furthermore, the same algorithm is extended to realize modulo 2n+1 multiply-add units. The derived partial products are reduced by an inverted end around carry-save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The performance and efficiency of the proposed multipliers are evaluated and compared against the earlier modulo 2n+1 multipliers, based on a single gate level model. Comparisons based on experimental CMOS implementations for both the multiply and multiply-add units are also given. The proposed multipliers yield area and power savings by an average of 15% and 10% respectively, while the corresponding area and power savings of the proposed multiply-add units are 14% and 21% respectively.

Design of High speed Modified Booth Encoded Parallel Multiplier

Design of High speed Modified Booth Encoded Parallel Multiplier

Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier

paper a method to build a faster array multiplier based on Radix 4 Modified Booth Encoder - which is broadly used for the signed multiplication applications- with less area and power is presented. This is achieved by optimizing the overall interconnection delay in the partial product array and by scheming the most efficient Full Adder and Booth Encoder in Complementary Pass Transistor Logic approach. The proposed array multiplier's performance in terms of delay, power and area is compared with conventional as well as Baugh-Wooley Multiplier. In order to optimize the power and area of the multiplier, a CPL Based MBE with standard partial product array is proposed and designed in full custom style. The use of efficient 10 Transistor based Full adders based on CPL logic ensures that the entire design is in CPL logic, which provides a regular outline with less interconnection intricacy.

A Spurious-Power Suppression technique for a Low-Power Multiplier

This paper presents the design exploration of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low- power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. Keywords-Booth encoder; low power; spurious power suppression technique(SPST); SPST-Adder.

A Novel 10-Transistor Encoder Design for Modified Booth Encoder to Optimize Power and Area

The aim of this paper is to reduce power and area of the Modified Booth Encoder. The encoders of the multiplier are implemented with Pass transistor XOR-XNOR block instead of two separate XOR and XNOR gates. The encoder consists of one XOR and XNOR with common inputs. The proposed encoder is designed with one XOR with two inputs and two outputs. Between two outputs, one is taken at before an inverter, the function is XNOR. Second is taken at after the inverter for XOR function. Due to this the proposed design eliminates two transistors. Hence this design consumes 47% and 77% less power than Pass Transistor XOR-XNOR [11] and CMOS XOR-XNOR respectively and also occupies less area. The results are obtained using H-spice at 2.0V for 180nm technology

A New Reduced Multiplication Structure for Low Power and Low Area Modified Booth Encoding Multiplier

This paper propose a new method for adding of sums and carries at the final stage of the Modified Booth Encoding (MBE) multiplier. In a conventional multiplier final stage, i.e carry propagate adder is used to add sums and carries. After partial product reduction these sums and carries are generated. In this method Carry Save Adder (CSA) is used to reduce the partial products generated by encoder and decoder. The carry generated by a column is fed to the input of a first adder of the next column on left side of the CSA and so on for few columns on Most Significant Bit (MSB) side. Due to removal of the few Adders, the proposed MBE 8x8 multiplier consumes less power, occupies less area, and operates at low voltages i.e at 1.0V. H-Spice is used to carry out the results for 180nm CMOS technology.

High Accuracy Fixed Width Multipliers using Modified Booth Algorithm

In this paper, using Radix-4 Modified Booth Encoding (MBE) algorithm high accuracy fixed width multiplier is developed. It keeps the input and output width same by truncating the n-least significant output bits. Post truncated multiplier (PTM) with regular partial product array; fewer partial product rows are generated. By slightly modifying this partial product matrix of Booth multiplication, error compensation value is calculated using error compensation generator. These values are added to the carry inputs of reserved adder cells to reduce the truncation error of fixed width multiplier. Compared with the existing circuits, the proposed error compensation generator results in reduction in mean error and mean-square error. This proposed method is applied to multiply and accumulate (MAC) unit which is the key operation for digital signal processing (DSP) systems and multimedia information processing efficiently compared to existing circuits. MAC performance is compared and analyzed with existing circuits. Technique is implemented in VHDL, simulated using MODELSIM and synthesized using Xilinx ISE.

Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations

This paper presents design of a novel high speed booth encoder-decoder in a 0.35µm CMOS technology. Focusing on transistor level implementation of the new architecture and employing newly designed truth table, the gate level delay of the whole system is reduced to one logic gate plus one transistor delay which is the main advantage of the proposed circuit. Simulation results indicate high speed performance of the designed circuit and depict low power dissipation feature of implemented architecture which makes this work suitable for extensive use in high speed arithmetic blocks.

Efficient modulo 2 n±1 squarers

Modulo 2 n ±1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2 n +1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32×32, two 16×16 or four 8×8 signed multiply-accumulation. Experimentally, when implemented with a 130nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.

Modified Booth Multipliers With a Regular Partial Product Array

The conventional modified Booth encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple approach is proposed to generate a regular partial product array with fewer partial product rows and negligible overhead, thereby lowering the complexity of partial product reduction and reducing the area, delay, and power of MBE multipliers. The proposed approach can also be utilized to regularize the partial product array of posttruncated MBE multipliers. Implementation results demonstrate that the proposed MBE multipliers with a regular partial product array really achieve significant improvement in area, delay, and power consumption when compared with conventional MBE multipliers.

MODIFIED MULTIPLY-ACCUMULATE ARCHITECTURE WITH THE SWITCHING POWER SWIFTNESS IMPROVEMENT TECHNIQUE

This paper presents a 32-bit multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The MAC architecture is multiplexing into the partial product generation and by inserting partial product in the carry chain of the reduction tree and the final carry-propagate adder. This Switching Power Swiftness Improvement Technique (SPSIT) has been applied on both the compression tree of the multipliers and the modified Booth Encoder to enlarge the power swiftness, for high-speed and low-power purposes. To filter out the spurious switching power of the MAC unit, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of LP multipliers after the data transition has been proposed. The SPSIT approach leads to a 40% power consumption reduction and speed improvement when compared with the other power minimization technique. This is an example of “shared egmentation” in which the existing scalar structure is segmented and then shared between vector modes. The MAC is area efficient, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors.