Modern Semiconductor Manufacturing Research Articles

Dynamic mode decomposition with memory.

This study proposed a numerical method of dynamic mode decomposition with memory (DMDm) to analyze multidimensional time-series data with memory effects. The memory effect is a widely observed phenomenon in physics and engineering and is considered to be the result of interactions between the system and environment. Dynamic mode decomposition (DMD) is a linear operation-based, data-driven method for multidimensional time-series data proposed in 2008. Although DMD is a successful method for time-series data analysis, it is based on ordinary differential equationsand thus cannot incorporate memory effects. In this study, we formulated the abstract algorithmic structure of DMDm and demonstrate its utility in overcoming the memoryless restriction imposed by existing DMD methods on the time-evolution model. In the numerical demonstration, we utilized the Caputo fractional differential to implement an example of DMDm such that the time-series data could be analyzed with power-law memory effects. Thus, we developed a fractional DMD, which is a DMD-based method with arbitrary (real value) order differential operations. The proposed method was applied to synthetic data from a set of fractional oscillators and model parameters were estimated successfully. The proposed method is expected to be useful for scientific applications and aid in model estimation, control, and failure detection of mechanical, thermal, and fluid systems in factory machines, such as modern semiconductor manufacturing equipment.

Detection and identification of particles on silicon wafers based on light scattering and absorption spectroscopy and Machine learning

Modern semiconductor manufacturing technology have a high-quality requirement of the wafers, and therefore the wafer inspection technique becomes increasingly important. During the manufacturing processes, particles can attach on the surface of the wafer which is an important factor of the quality and can even make it impossible to use the wafer. In this research, we introduce a particle detection and identification method based on the scattering and absorption spectra of the particles. A machine learning algorithm was developed to capture the feature of the particles and is able to identify the particle material from the scattering spectrum. Three different particles (Al2O3, SiC, and Si) were used to test this system. The validation accuracy achieves higher than 98% after 5 iterations training. The system was tested by scattering these three particles on the same wafer in different regions without mixing with each other. The results shows that particle Al2O3 and Si were identified with a high accuracy, whereas it is still challenging for the system to correctly label SiC particles. This can be improved by a larger dataset to enhance the generalization ability of the machine learning model.

Multi-spectral snapshot diffraction-based overlay metrology.

Diffraction-based overlay (DBO) metrology has been successfully introduced to deal with the tighter overlay control in modern semiconductor manufacturing. Moreover, DBO metrology typically needs to be performed at multiple wavelengths to achieve accurate and robust measurement in the presence of overlay target deformations. In this Letter, we outline a proposal for multi-spectral DBO metrology based on the linear relation between the overlay errors and the combinations of off-diagonal-block Mueller matrix elements ΔM = Mij - ( - 1)jMji (i = 1, 2; j = 3, 4) associated with the zeroth-order diffraction of overlay target gratings. We propose an approach that can realize snapshot and direct measurement of ΔM over a broad spectral range without any rotating or active polarization component. The simulation results demonstrate the capability of the proposed method for multi-spectral overlay metrology in a single shot.

A Fine-Grained, End-to-End Feature-Scale CMP Modeling Paradigm Based on Fully Convolutional Neural Networks

Chemical mechanical polishing (CMP) planarizes the chip surface through a synergistic effect of chemical etching and abrasive polishing, and has become increasingly essential in modern semiconductor manufacturing. For better production yield, the industry seeks an accurate CMP model to identify, localize and control surface unevenness caused by the layout dependent effect (LDE) prior to fabrication, which provides valuable information for manufacturing-friendly designs, such as accurate hotspot prediction, design-rule optimization, and smart dummy fill. However, existing models are often overly coarse-grained and inaccurate: They are unable to utilize or analyze detailed topology information in a layout design, and can only characterize the post-CMP chip surface into a rough step-height model. The prediction resolution is also constrained by the featuring window size. In this paper, we propose a novel fine-grained and end-to-end feature-scale CMP modeling paradigm based on fully convolutional neural networks. The model directly analyzes the detailed layout topology without an explicit step of featuring parameter extraction, accurately predicts the rich chip surface micro-topography at a feature-scale precision. We designed and taped-out test chips under 28nm and 40nm processes. Experiments on silicon data demonstrated our model’s accuracy improvements of 65% to 76%, as well as its cross-process-node adaptability.

A general tool-based multi-product model for high-mixed production in semiconductor manufacturing

Concerning the high-mixed nature in modern semiconductor manufacturing, the original ‘tool-based’ exponentially weighted moving average (EWMA) controller is proved to be unstable when the plant-model mismatches are diverse for different products, leading to large variations and lots of wastes. Hence, this paper proposes a general multi-product model for ‘tool-based’ EWMA control. The core of the model lies in the algorithm on how to estimate the noise disturbance accurately, i.e. the noise is considered as the sum of the following two parts: the estimated noise after the thread has been processed in the last cycle and the cumulative noise during the period when the thread is not on production between the two cycles. In this way, the production for a particular thread is isolated from that of others to avoid instability existing in the traditional tool-based EWMA control. Superiorities of the proposed model are demonstrated through theoretical analysis, simulation experiment and industrial case study.

Evolution of lithography-to-etch bias in multi-patterning processes

Quantitatively accurate, physics-based, computational modeling of etching and lithography processes is essential for modern semiconductor manufacturing. This paper presents lithography and etch models for a trilayer process in a back end of the line manufacturing vehicle. These models are calibrated and verified against top-down scanning electron microscope (SEM) and cross-sectional SEM measurements. Calibration errors are within 2 nm, while the maximum verification error is less than 3 nm. A fluorocarbon plasma etch of the spin-on-glass (SOG) layer accounts for most of the etch bias present in the process. The tapered profile in the SOG etch step is generated due to the polymerization process by fluorocarbon radicals generated in the plasma. The model predicts a strong correlation between the etch bias in the SOG etch step and the neutral-to-ion flux ratio in the plasma. The second etch step of the flow, which etches the spin-on-carbon (SOC) layer using an H2/N2 plasma, results in a negative etch bias (increase in CDs) for all measured features. The ratio of hydrogen to nitrogen radical fluxes effectively controls the etch bias in this step, with the model predicting an increase in the etch bias from negative to positive values as the H-to-N ratio decreases. The model also indicates an aspect ratio dependent etch rate in the SOG and SOC etch steps, as seen in the etch front evolution in a three-dimensional test feature. The third and final step of the process, SiO2-etch, generates an insignificant etch bias in all the test structures. Finally, the accuracy of the etch simulations is shown to be dependent on the accuracy of the incoming photoresist shapes. Models that consider only the top-down SEM measurement as input and do not account for an accurate photoresist profile, suffered significant errors in the post-etch CD predictions.

Short-Term Scheduling Model of Cluster Tool in Wafer Fabrication

Since last decade, the cluster tool has been mainstream in modern semiconductor manufacturing factories. In general, the cluster tool occupies 60% to 70% of production machines for advanced technology factories. The most characteristic feature of this kind of equipment is to integrate the relevant processes into one single machine to reduce wafer transportation time and prevent wafer contaminations as well. Nevertheless, cluster tools also increase the difficulty of production planning significantly, particularly for shop floor control due to complicated machine configurations. The main objective of this study is to propose a short-term scheduling model. The noteworthy goal of scheduling is to maximize the throughput within time constraints. There are two modules included in this scheduling model—arrival time estimation and short-term scheduling. The concept of the dynamic cycle time of the product’s step is applied to estimate the arrival time of the work in process (WIP) in front of machine. Furthermore, in order to avoid violating the time constraint of the WIP, an algorithm to calculate the latest time of the WIP to process on the machine is developed. Based on the latest process time of the WIP and the combination efficiency table, the production schedule of the cluster tools can be re-arranged to fulfill the production goal. The scheduling process will be renewed every three hours to make sure of the effectiveness and good performance of the schedule.

SMT2020—A Semiconductor Manufacturing Testbed

We present a new set of simulation models, organized in a testbed. The aim of the testbed consists in providing researchers with a platform able to credibly represent the complexity of modern semiconductor manufacturing. The testbed is open to public use, and include so far four models. A high-volume/low-mix model and a low-volume/high-mix model constitutes the foundation of the testbed. Two additional models incorporate the complexity of engineering lots. We conclude this paper by presenting a case study that demonstrates that the third and fourth model can be used to assess the performance of integrated dispatching strategies for production and engineering lots.

A Lagrangian heuristic for minimising risk using multiple heterogeneous metrology tools

Motivated by the high investment and operational metrology cost, and subsequently the limited metrology capacity, in modern semiconductor manufacturing facilities, we model and solve the problem of optimally assigning the capacity of several imperfect metrology tools to minimise the risk in terms of expected product loss on heterogeneous production machines. In this paper, metrology tools can differ in terms of reliability and speed. The resulting problem can be reduced to a variant of the Generalized Assignment Problem (GAP), the Multiple Choice, Multiple Knapsack Problem (MCMKP). A Lagrangian heuristic, including multiple feasibility heuristics, is proposed to solve the problem that are tested on randomly generated instances.

Decomposition without aggregation for performance approximation in queueing network models of semiconductor manufacturing

Accurate and speedy forecasts of production cycle time are key components that support the operation of modern semiconductor wafer fabricators. Estimates of cycle time can be obtained via simulation, but such an approach, though common, requires significant computational investment and model maintenance. Queueing network models and approximations for their performance can provide a viable alternative. As modern semiconductor manufacturing systems exhibit largely reentrant product routing, but contain essential probabilistic routes (for metrology and rework), prior mean cycle time approximation methods are not well suited to the system structure. In this paper, we extend the decomposition without aggregation (DWOA) approach – which is tailored to systems with deterministic routing – to allow for the existence of probabilistic paths. Numerical and simulation studies are conducted with numerous practically inspired datasets to assess the quality of the resulting mean cycle time approximations. The results reveal that our approach outperforms the existing mean cycle time approximations on datasets inspired by the semiconductor industry MIMAC benchmark datasets. For example, in MIMAC dataset 1, our mean cycle time approximations exhibit an average of 10.33% error compared to 18.82% error for existing approaches.

Statistical Process Control for Monitoring the Particles With Excess Zero Counts in Semiconductor Manufacturing

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations.

Application of Neural Network-Based Oxide Deposition Models to CMP Modeling

Numerous deposition processes are used in modern semiconductor manufacturing, including high-density plasma chemical vapor deposition (HDP-CVD), spin-on dielectric (SOD), flowable CVD (FCVD), and enhanced high aspect ratio processes (eHARP). Generation of high quality post-deposition surface profiles is crucial for chemical-mechanical planarization (CMP) model building, due to the complex nature of the CMP process and long-range effects in CMP. Measurements show complicated post-deposition surface profile height dependence on the underlying pattern for these deposition processes. While high-quality compact models exist for HDP-CVD and SOD processes, building compact models for FCVD and eHARP is a challenge, since they include several deposition and annealing steps, and show complicated behavior width respect to the underlying pattern. In this paper, we present the application of neural networks (NNs) to post-deposition surface profiles modeling for the above-mentioned deposition processes. Experiments showed that NNs should have at least two hidden layers and 6–10 neurons per hidden layer to capture the complexity of deposited surface profiles. The application of NNs to modeling surface profiles of deposition processes has shown that NNs provide a general approach for modeling surface profiles of deposition processes without long-range effects for CMP modeling, irrespective of the complexity of the deposition process.

Subresolution Assist Feature Generation With Supervised Data Learning

Subresolution assist feature (SRAF) generation is a very important resolution enhancement technique to improve yield in modern semiconductor manufacturing process. Model-based and rule-based approaches are widely adopted in the semiconductor industry. The model-based SRAF generation can achieve a high accuracy but it is known to be time-consuming and it is hard to obtain consistent SRAFs on the same layout pattern configurations. The rule-based SRAF generation is highly technology dependent and it is becoming extremely difficult to render high-quality results in advanced technology nodes. This paper proposes supervised data learning techniques for fast yet consistent SRAF generation with high-quality results. We first propose the constrained concentric circle with area sampling scheme for feature extraction. Illumination source symmetry-based feature compaction technique is further invented to reduce the training data set size and achieve consistent SRAF predictions. Using accurate model-based SRAFs as training data, classification models based on logistic regression (LGR) and support vector machine are calibrated for SRAF predictions. Moreover, the probability maximum prediction is proposed to generate manufacturing-friendly SRAFs with a greedy simplification scheme. We compare support vector machine and LGR models by embedding into an entire mask optimization flow, where the support vector machine model obtains better lithographic performance. Experimental results demonstrate that, compared with the commercial Calibre tool, supervised data learning techniques for SRAF generation obtain significant speed up (>3X for a ${100~{ {{\mathrm{um}}} }^{2}}$ layout clip) and comparable lithographic performance in terms of edge placement error and process variation band.

(Invited) Research to Manufacturing: ALD Design for Precision Atomic Layer Fabrication

Novel atomic layer engineering technologies have emerged as key developmental tools for <2X node fabrication in the modern semiconductor manufacturing. Today’s applications include front-end-of-line (FEOL) spacers and liners, isolation gapfill, FinFET conformal doping, multi-patterning layers, through-silicon via liners, sacrificial layers, encapsulation, selective deposition/etch, conformal etch, and surface smoothening to name a few. In the first section, industrial drivers including intelligent devices, economics, and inflection points will be correlated to atomic layer engineering market applications. The advantageous qualities of self-limiting and saturation technologies will be reviewed with a focus on implications for throughput, unit film property optimization, and controlling process variation. An alternative paradigm shift for processing in the “sub-saturated regime” will be reviewed with attention to the pros and cons. The complementary nature of ALD and ALE will be considered with a predictive look at the future of atomic layer engineering.

Editorial Kudos to Our Reviewers

The people that we depend on to review the manuscripts published in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Transactions on Semiconductor Manufacturing</i> ensure that work of the highest quality ends up in each finished paper. Often this requires more than one detailed reading of a manuscript that is separated by several weeks from the previous one. The reviewers are all recognized experts in their fields. Despite the demands to fulfill the duties of their employers they set aside time to support the broad dissemination of the latest results on factory and manufacturing integration, process control, yield enhancement and modeling, metrology, photolithography, factory modeling and control, and equipment technology—all of the areas that go into a modern semiconductor manufacturing facility. I personally thank all of the contributions that our reviewers have made in 2016. We would not have a journal that is a leading source of information on semiconductor manufacturing without this selfless effort.

Editorial Kudos to Our Reviewers

The people that we depend on to review the manuscripts published in the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING ensure that work of the highest quality ends up in each finished paper. Often this requires more than one detailed reading of a manuscript that is separated by several weeks from the previous one. The reviewers are all recognized experts in their fields. Despite the demands to fulfill the duties of their employers, they set aside time to support the broad dissemination of the latest results on factory and manufacturing integration, process control, yield enhancement and modeling, metrology, photolithography, factory modeling and control, and equipment technology—all of the areas that go into a modern semiconductor manufacturing facility. I personally thank all of the contributions that our reviewers have made in 2015. We would not have a journal that is a leading source of information on semiconductor manufacturing without this selfless effort.

Technology modules from micro- and nano-electronics for the life sciences.

The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website.

A mathematical programming approach for optimizing control plans in semiconductor manufacturing

In a globally competitive environment, sustaining high yield with a minimum number of quality controls is key for manufacturing plants to remain competitive. In modern semiconductor manufacturing facilities, with the moves to ever smaller geometries and the variety among products to be run concurrently, designing efficient control plans is becoming increasingly complex. Since a 100% of inspection is neither feasible nor interesting because of the cost and reliability of each control, dynamically identifying the right product to inspect is one of the keys to achieve high yield and reduce the cycle time. However, when control parameters are over- or under-estimated, a dynamic sampling static sampling strategy can lead to poor results. In this paper we propose an integer linear programming approach to optimize the use of inspection capacity through dynamic sampling. The goal is to determine two key parameters (called warning limit and inhibit limit) that are related to the resulting level of risk and the available inspection capacity. The model has been implemented on a commercial solver and tested using actual industrial data. Results show that the overall risk can be strongly reduced without any additional capacity.

A practical method for optical dispersion model selection and parameters variations in scatterometry analysis with variable n&k's

Optical critical dimension (OCD) scatterometry in recent years became a well-accepted and powerful technique to determine the properties and grating profiles of 2D and 3D microelectronic structures (critical dimensions, side-wall angles, grating and underlying thin film thicknesses) in modern semiconductor manufacturing. However, the optical scatterometry, as any model-based metrology technique, relies on the accuracy of the OCD model which highly depends on the optical properties (the n&k's) of the materials in the structure. In practice, even small deviations in material's optical properties (from nominal model inputs) due to process condition variations might significantly affect the scatterometry measurements. A logical way to deal with this problem is to allow some degree of the n&k's variability of the most affected layer(s) in the OCD model describable by relevant dispersion model(s) (floating n&k's). Essentially, one of the largest complications for the end users (process engineers) is to decide which optical dispersion model (Cauchy, Lorentz, Tauc–Lorentz, etc.) needs to be selected to describe a material under production conditions and which parameters are more sensitive and need to be floated in the OCD model. We developed an approach which, we believe, will result in more straightforward and fast development of the OCD models. This approach provides a possibility to automatically select a most proper dispersion model which has been always an ambiguous decision for most of the end users. This methodology will allow determination of most influential model parameters to vary, eliminating potential sources of modeling error at the initial steps of the OCD modeling. A few examples to illustrate the key ideas and practical use of our procedure have been provided.

Analysis and modeling of the optical endpoint signal for precision etching

Endpoint detection is an essential methodology for process control in dry etching for modern semiconductor manufacturing technology. In this paper, an analysis has been performed on the factors, such as the local etch rate, the local film thickness differences, and the open area and the global uniformities of the etch rate and film thickness, affecting the change in the optical emission endpoint signals on a patterned device wafer. Also, a model of the endpoint signal evolution, which includes an effective open ratio, the ratio of the relative open area after considering the local difference in the etch rate and the film thickness to the total open area at the very beginning of the etch process, has been established. Compared to the conventional open ratio, which is the ratio derived from the reticle used for lithography, the effective open ratio is better in explaining and predicting the endpoint signal change. The effective open ratio can be used to design dummy patterns that are used to improve endpoint detection in critical dry etch processes such as gate cuts in logic gate formation, etc.