Modern Multi-core Systems Research Articles

Special edition on resource partitioning for modern multicore systems

Special edition on resource partitioning for modern multicore systems

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration

DRAM memory is a performance bottleneck for many applications, due to its high access latency. Previous work has mainly focused on data locality, introducing small but fast regions to cache frequently accessed data, thereby reducing the average latency. However, these locality-based designs have three challenges in modern multi-core systems: (1) inter-application interference leads to random memory access traffic, (2) fairness issues prevent the memory controller from over-prioritizing data locality, and (3) write-intensive applications have much lower locality and evict substantial dirty entries. With frequent data movement between the fast in-DRAM cache and slow regular arrays, the overhead induced by moving data may even offset the performance and energy benefits of in-DRAM caching. In this article, we decouple the data movement process into two distinct phases. The first phase is Load-Reduced Destructive Activation (LRDA), which destructively promotes data into the in-DRAM cache. The second phase is Delayed Cycle-Stealing Restoration (DCSR), which restores the original data when the DRAM bank is idle. LRDA decouples the most time-consuming restoration phase from activation, and DCSR hides the restoration latency through prevalent bank-level parallelism. We propose FASA-DRAM, incorporating destructive activation and delayed restoration techniques to enable both in-DRAM caching and proactive latency-hiding mechanisms. Our evaluation shows that FASA-DRAM improves the average performance by 19.9% and reduces average DRAM energy consumption by 18.1% over DDR4 DRAM for four-core workloads, with less than 3.4% extra area overhead. Furthermore, FASA-DRAM outperforms state-of-the-art designs in both performance and energy efficiency.

Fast, parallel, and cache-friendly suffix array construction

PurposeString indexes such as the suffix array (sa) and the closely related longest common prefix (lcp) array are fundamental objects in bioinformatics and have a wide variety of applications. Despite their importance in practice, few scalable parallel algorithms for constructing these are known, and the existing algorithms can be highly non-trivial to implement and parallelize.MethodsIn this paper we present caps-sa, a simple and scalable parallel algorithm for constructing these string indexes inspired by samplesort and utilizing an LCP-informed mergesort. Due to its design, caps-sa has excellent memory-locality and thus incurs fewer cache misses and achieves strong performance on modern multicore systems with deep cache hierarchies.ResultsWe show that despite its simple design, caps-sa outperforms existing state-of-the-art parallel sa and lcp-array construction algorithms on modern hardware. Finally, motivated by applications in modern aligners where the query strings have bounded lengths, we introduce the notion of a bounded-context sa and show that caps-sa can easily be extended to exploit this structure to obtain further speedups. We make our code publicly available at https://github.com/jamshed/CaPS-SA.

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration

DRAM memory is a performance bottleneck for many applications, due to its high access latency. Previous work has mainly focused on data locality, introducing small-but-fast regions to cache frequently accessed data, thereby reducing the average latency. However, these locality-based designs have three challenges in modern multi-core systems: 1) Inter-application interference leads to random memory access traffic. 2) Fairness issues prevent the memory controller from over-prioritizing data locality. 3) Write-intensive applications have much lower locality and evict substantial dirty entries. With frequent data movement between the fast in-DRAM cache and slow regular arrays, the overhead induced by moving data may even offset the performance and energy benefits of in-DRAM caching. In this paper, we decouple the data movement process into two distinct phases. The first phase is Load-Reduced Destructive Activation (LRDA), which destructively promotes data into the in-DRAM cache. The second phase is Delayed Cycle-Stealing Restoration (DCSR), which restores the original data when DRAM bank is idle. LRDA decouples the most time-consuming restoration phase from activation, and DCSR hides the restoration latency through prevalent bank-level parallelism. We propose FASA-DRAM incorporating destructive activation and delayed restoration techniques to enable both in-DRAM caching and proactive latency-hiding mechanisms. Our evaluation shows that FASA-DRAM improves the average performance by 19.9% and reduces average DRAM energy consumption by 18.1% over DDR4 DRAM for four-core workloads, with less than 3.4% extra area overhead. Furthermore, FASA-DRAM outperforms state-of-the-art designs in both performance and energy efficiency.

ConsICA: an R package for robust reference-free deconvolution of multi-omics data.

Deciphering molecular signals from omics data helps understanding cellular processes and disease progression. Effective algorithms for extracting these signals are essential, with a strong emphasis on robustness and reproducibility. R/Bioconductor package consICA implements consensus independent component analysis (ICA)-a data-driven deconvolution method to decompose heterogeneous omics data and extract features suitable for patient stratification and multimodal data integration. The method separates biologically relevant molecular signals from technical effects and provides information about the cellular composition and biological processes. Build-in annotation, survival analysis, and report generation provide useful tools for the interpretation of extracted signals. The implementation of parallel computing in the package ensures efficient analysis using modern multicore systems. The package offers a reproducible and efficient data-driven solution for the analysis of complex molecular profiles, with significant implications for cancer research. The package is implemented in R and available under MIT license at Bioconductor (https://bioconductor.org/packages/consICA) or at GitHub (https://github.com/biomod-lih/consICA).

Parallel and Flexible Dynamic Programming via the Mini-Batch Bellman Operator

The Bellman operator constitutes the foundation of dynamic programming (DP). An alternative is presented by the Gauss-Seidel operator, whose evaluation, differently from that of the Bellman operator where the states are all processed at once, updates one state at a time, while incorporating into the computation the interim results. The provably better convergence rate of DP methods based on the Gauss-Seidel operator comes at the price of an inherent sequentiality, which prevents the exploitation of modern multi-core systems. In this work we propose a new operator for dynamic programming, namely, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mini-batch Bellman operator</i> , which aims at realizing the trade-off between the better convergence rate of the methods based on the Gauss-Seidel operator and the parallelization capability offered by the Bellman operator. After the introduction of the new operator, a theoretical analysis for validating its fundamental properties is conducted. Such properties allow one to successfully deploy the new operator in the main dynamic programming schemes, such as value iteration and modified policy iteration. We compare the convergence of the DP algorithm based on the new operator with its earlier counterparts, shedding light on the algorithmic advantages of the new formulation and the impact of the batch-size parameter on the convergence. Finally, an extensive numerical evaluation of the newly introduced operator is conducted. In accordance with the theoretical derivations, the numerical results show the competitive performance of the proposed operator and its superior flexibility, which allows one to adapt the efficiency of its iterations to different structures of MDPs and hardware setups.

RabbitQCPlus 2.0: More efficient and versatile quality control for sequencing data.

Assessing the quality of sequencing data plays a crucial role in downstream data analysis. However, existing tools often achieve sub-optimal efficiency, especially when dealing with compressed files or performing complicated quality control operations such as over-representation analysis and error correction. We present RabbitQCPlus, an ultra-efficient quality control tool for modern multi-core systems. RabbitQCPlus uses vectorization, memory copy reduction, parallel (de)compression, and optimized data structures to achieve substantial performance gains. It is 1.1 to 5.4 times faster when performing basic quality control operations compared to state-of-the-art applications yet requires fewer compute resources. Moreover, RabbitQCPlus is at least 4 times faster than other applications when processing gzip-compressed FASTQ files and 1.3 times faster with the error correction module turned on. Furthermore, it takes less than 4 minutes to process 280 GB of plain FASTQ sequencing data, while other applications take at least 22 minutes on a 48-core server when enabling the per-read over-representation analysis. C++ sources are available at https://github.com/RabbitBio/RabbitQCPlus.

Evaluation of the efficiency of implementation of asynchronous computing algorithms using coroutines and threads in С++

Modern multi-core systems are most effective when used in large server centers and for cloud computing. However, despite the known complexity of software implemen-tation, parallel computing on multiprocessors is increasingly used in computer model-ling. Advanced mechanisms of synchronous and multithreaded programming are in-creasingly used to improve the productivity of numerical studies, reducing the time of computer models implementation. One such mechanism is coroutines, a convenient tool for managing asynchronous operations introduced in the C++20 standard. A special feature of coroutines is the ability to suspend a function at a certain stage, saving its state, and after some time resume its execution from the previous stop. The aim of this research is to improve the performance of computer modelling by using coroutines and data threads. As a result of the work, a test algorithm for multiplying a matrix by a vector and its modified asynchronous version using the coroutine mechanism and splitting into two data threads was developed, which allowed to achieve 1.94 times increase in the com-puting speed when the matrix dimension is 15000 (2.25×106 elements). It has been found that at a small matrix dimension, the developed asynchronous algorithm using coroutines and splitting into two threads is less efficient than the single thread algo-rithm. This is due to the fact that the compiler needs some time to create threads and start execution simultaneously. With a large dimensionality, the performance of the asynchronous algorithm increases significantly. With a matrix dimension of more than 1200, the use of an asynchronous algorithm divided into two threads is guaranteed to be more efficient than a single-threaded. The data obtained are consistent with the results of similar studies of the problem of increasing the efficiency of computer modelling using alternative software and hard-ware. The new method of solving the problems of asynchronous programming provides a more efficient and simple mechanism for managing asynchronous operations.

RabbitFX: Efficient Framework for FASTA/Q File Parsing on Modern Multi-Core Platforms.

The continuous growth of generated sequencing data leads to the development of a variety of associated bioinformatics tools. However, many of them are not able to fully exploit the resources of modern multi-core systems since they are bottlenecked by parsing files leading to slow execution times. This motivates the design of an efficient method for parsing sequencing data that can exploit the power of modern hardware, especially for modern CPUs with fast storage devices. We have developed RabbitFX, a fast, efficient, and easy-to-use framework for processing biological sequencing data on modern multi-core platforms. It can efficiently read FASTA and FASTQ files by combining a lightweight parsing method by means of an optimized formatting implementation. Furthermore, we provide user-friendly and modularized C++ APIs that can be easily integrated into applications in order to increase their file parsing speed. As proof-of-concept, we have integrated RabbitFX into three I/O-intensive applications: fastp, Ktrim, and Mash. Our evaluation shows that the inclusion of RabbitFX leads to speedups of at least 11.6 (6.6), 2.4 (2.4), and 3.7 (3.2) compared to the original versions on plain (gzip-compressed) files, respectively. These case studies demonstrate that RabbitFX can be easily integrated into a variety of NGS analysis tools to significantly reduce associated runtimes. It is open source software available at https://github.com/RabbitBio/RabbitFX.

Scalable and Robust Snapshot Isolation for High-Performance Storage Engines

MVCC-based snapshot isolation promises that read queries can proceed without interfering with concurrent writes. However, as we show experimentally, in existing implementations a single long-running query can easily cause transactional throughput to collapse. Moreover, existing out-of-memory commit protocols fail to meet the scalability needs of modern multi-core systems. In this paper, we present three complementary techniques for robust and scalable snapshot isolation in out-of-memory systems. First, we propose a commit protocol that minimizes cross-thread communication for better scalability, avoids touching the write set on commit, and enables efficient fine-granular garbage collection. Second, we introduce the Graveyard Index, an auxiliary data structure that moves logically-deleted tuples out of the way of operational transactions. Third, we present an adaptive version storage scheme that enables fast garbage collection and improves scan performance of frequently-modified tuples. All techniques are engineered to scale well on multi-core processors, and together enable robust performance for complex hybrid workloads.

A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints

In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side-channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software-based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines.

Online Power Management for Multi-Cores: A Reinforcement Learning Based Approach

Power and energy is the first-class design constraint for multi-core processors and is a limiting factor for future-generation supercomputers. While modern processor design provides a wide range of mechanisms for power and energy optimization, it remains unclear how software can make the best use of them. This article presents a novel approach for runtime power optimization on modern multi-core systems. Our policy combines power capping and uncore frequency scaling to match the hardware power profile to the dynamically changing program behavior at runtime. We achieve this by employing reinforcement learning (RL) to automatically explore the energy-performance optimization space from training programs, learning the subtle relationships between the hardware power profile, the program characteristics, power consumption and program running times. Our RL framework then uses the learned knowledge to adapt the chip's power budget and uncore frequency to match the changing program phases for any new, previously unseen program. We evaluate our approach on two computing clusters by applying our techniques to 11 parallel programs that were not seen by our RL framework at the training stage. Experimental results show that our approach can reduce the system-level energy consumption by 12 percent, on average, with less than 3 percent of slowdown on the application performance. By lowering the uncore frequency to leave more energy budget to allow the processor cores to run at a higher frequency, our approach can reduce the energy consumption by up to 17 percent while improving the application performance by 5 percent for specific workloads.

Accelerated K-Means Algorithms for Low-Dimensional Data on Parallel Shared-Memory Systems

This paper considers the problem of exact accelerated algorithms for the K-means clustering of low-dimensional data on modern multi-core systems. A version of the filtering algorithm parallelized using the OpenMP (Open Multi-Processing) standard is proposed. The algorithm employs a kd-tree structure to skip some unnecessary calculations between cluster centroids and feature vectors. In our approach, both the kd-tree construction and the iterations of the K-means are parallelized using the OpenMP tasking mechanism. A new task is created for a recursive call performed during kd-tree construction and traversal. The tasks are executed in parallel by the cores of a shared-memory system. In computational experiments, we evaluated the parallel efficiency of our approach and compared its performance to the parallel Lloyd’s method, a GPU (Graphics Processing Unit) formulation of the K-means algorithm, and two parallel triangle inequality-based algorithms intended for low-dimensional data. The evaluation was performed on six synthetic datasets from two distributions and seven real-life datasets. The experiments, executed on a 24-core system, indicated that our version of the filtering algorithm had satisfactory or high parallel efficiency. Its runtime was much shorter than those of competing algorithms. However, the advantage of the parallel filtering algorithm decreased rapidly as the dimension of data increased.

Multi-core processors use for numerical problems solutions

Problem statement. The use of programming technologies on modern multicore systems is an integral part of an enterprise whose activities involve multitasking or the need to make a large number of calculations over a certain time. The article discusses the development of such technologies aimed at increasing the speed of solving various issues, for example, numerical modeling.Objective. Search for alternative ways to increase the speed of calculations by increasing the number of processors. As an example of increasing the calculation speed depending on the number of processors, the well-known heat-transfer equation is taken, and classical numerical schemes for its solution are given. The use of explicit and implicit schemes is compared, including for the possibility of parallelization of calculations.Results. The article describes systems with shared and distributed memory, describes their possible use for solving various problems, and provides recommendations for their use.Practical implications. Parallel computing helps to solve many problems in various fields, as it reduces the time required to solve partial differential equations.

TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler

Modern multicore systems, which perform complex functionalities on densely packed multi-million gate platforms at high frequencies, are often susceptible to inappropriate surges in core temperatures, if not effectively controlled. Increasing temperature above specified limits not only leads to high cost of cooling but also results in higher dissipation of leakage power together with a reduction in performance and lower system life expectancy. In this work, we propose a two-level low-overhead proportional fair resource allocation strategy called Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler (TARTS), for periodic real-time tasks to be executed on a thermally bounded multicore device. The proposed algorithm’s first level divides time into distinct slices based on deadlines of tasks, so that exact proportional fairness is maintained at all slice boundaries. The second level accomplishes intra-slice scheduling with the aim of maximising the use of resources while not breaching a specified thermal threshold. Experimental results show that our scheme can deliver a significantly higher resource usage efficiency compared to a baseline greedy approach, TA-MTS. For example, TARTS is able to achieve up to 42% higher task acceptance ratios compared to TA-MTS on a fully loaded quad-core system with 80 tasks and temperature threshold of 90 °C.

Evaluating the performance of atomic operations on modern multicore systems

In this work we analyse the efficiency of atomic operations compare-and-swap (CAS), fetch-and-add (FAA), swap (SWP), load and store on modern multicore processors. These operations implemented in hardware as processor instructions are highly demanded in multithreaded programming (design of thread locks and non-blocking data structures). In this article we study the influence of cache coherence protocol, size and locality of the data on the latency of the operations. We developed a benchmark for analyzing the dependencies of throughput and latency on these parameters. We present the results of the evaluation of the efficiency of atomic operations on modern x86-64 processors and give recommendations for the optimizations. Particularly we found atomic operations, which have minimum (load), maximum (“successful CAS”, store) and comparable (“unsuccessful CAS”, FAA, SWP) latency. We showed that the choice of a processor core to perform the operation and the state of cache-line impact on the latency at average 1.5 and 1.3 times respectively. The suboptimal choice of the parameters may increase the throughput of atomic operations from 1.1 to 7.2 times. Our evidences may be used in the design of new and optimization of existing concurrent data structures and synchronization primitives.

A Multicore Chip Load Model for PDN Analysis Considering Voltage–Current-Timing Interdependency and Operation Mode Transitions

Power consumption and current fluctuation are continuously increasing in modern multicore systems. Such current flow may cause severe supply noise via off-chip and on-chip power delivery networks (PDN). Unexpected noise impacts the chip delay performance or even causes malfunction. In traditional practice, PDN designers assume a simple current source-based chip load, but it is often oversimplified, where the load current is modeled only for one or a few operation modes, and it is constant irrelevant to supply noise. In this paper, we propose a new chip load model that enables even off-chip PDN designers to assess the noise impact on circuit performance and use realistic current profile under supply voltage noise. We also integrate a control signal interface so that the model can switch the processor operation modes for finding unexpected noise behavior in design time and pursuing robust PDN design. Experimental results show that the proposed model mostly described by Verilog-A reproduces the current profile, current peak, and timing data well even while it achieves over $300\times $ run-time reduction compared to a transistor-level model. We also experimentally demonstrate that a land-side capacitor is helpful to improve processor timing performance in our test case.

The time and energy efficiency of modern multicore systems

With the increasing adoption of homogeneous and heterogeneous shared-memory multicore systems, we aim to improve the understanding of their time and energy performance by extending the classic speedup laws proposed by Amdahl and Gustafson. We derive speedup equations for heterogeneous systems and introduce energy savings models for both homogeneous and heterogeneous multicores. These models use two key parameters, (i) the active power fraction (APF) of a core which represents the ratio between the core’s average active power and the power of the idle system, and (ii) the inter-core speedup (ICS) representing the difference in speed among different types of cores in a heterogeneous system. Using both modeling and measurements, we show that energy savings are achievable, but limited by the APF on systems with large core counts and by both the APF and workload’s sequential fraction on systems with low core counts. Our models are validated against measurements on modern multicore systems including two homogeneous servers with 48 cores which represent both traditional brawny x86/64 and emerging wimpy ARM nodes, and two heterogeneous wimpy systems with ARM big.LITTLE and NVIDIA Denver cores, respectively.

Maximizing Performance under a Power Constraint on Modern Multicore Systems

Energy efficiency and energy-proportional computing have become a central focus in modern supercomputers. These supercomputers should provide high throughput per unit of power to be sustainable in terms of operating cost and failure rates. In this paper, a power-bounded strategy is proposed that maximizes parallel application performance under a given power constraint. The strategy dynamically allocates power to core, uncore, and memory power domains within a node to maximize performance under a given power budget. Experiments on a 20-core Haswell-EP platform for a real-world parallel application GAMESS demonstrate that the proposed strategy delivers performance within 4% of the best possible performance for as much as 25% reduction in the minimum power budget required for maximum performance.

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power walls. In this trend, FPGA-based accelerators are becoming increasingly attractive, due to their excellent flexibility and low design cost. In this paper, we propose the architectural support for efficient interfacing between FPGA-based multi-accelerators and chip-multiprocessors (CMPs) connected through the network-on-chip (NoC). Distributed packet receivers and hierarchical packet senders are designed to maintain scalability and reduce the critical path delay under a heavy task load. A dedicated accelerator chaining mechanism is also proposed to facilitate intra-FPGA data reuse among accelerators to circumvent prohibitive communication overhead between the FPGA and processors. In order to evaluate the proposed architecture, a complete system emulation with programmability support is performed using FPGA prototyping. Experimental results demonstrate that the proposed architecture has high-performance, and is light-weight and scalable in characteristics.