Modern MOSFETs Research Articles

Evolution, Challenges and Applications of Modern MOSFETs

As technology scales down to the nanoscale regime, MOSFETs are widely used in various applications today, which serve as key components in power supplies, amplifiers, digital circuits, and microprocessors. Their ability to control and switch high currents makes them essential in electronic devices, ranging from smartphones and laptops to industrial machinery and electric vehicles. However, traditional MOSFET designs face significant limitations due to quantum effects, increased variability, and many other issues. They are prone to overheating, which limits their power handling capability, and their switching speeds are relatively slow, leading to inefficiencies in high-frequency circuits. Furthermore, traditional MOSFETs suffer from voltage limitations and require complex driver circuits, restricting their use in certain high-voltage applications. This paper provides a focused exploration of the challenges and opportunities in designing nanoscale MOSFETs, which starts from providing a comprehensive overview of the history, differences, dilemmas, and applications of modern MOSFETs. By examining the evolution of MOSFET technology, discussing the challenges faced by designers, and exploring the wide range of applications, which aims to inspire further research, innovation, and advancements in this critical field of electronics.

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%–30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.

Modeling and simulation of the charge trapping component of BTI and RTS

Charge trapping phenomena is known to be a major reliability concern in modern MOSFETS, playing a significant role in aging through Bias Temperature Instability (BTI) and dominating low-frequency noise behavior. An electrical level modeling and simulation approach, valid at DC, AC and transient operation conditions is presented. Detailed statistical analysis is provided, aiming at proper modeling of BTI and noise variability, as well as to facilitate the understanding of physical mechanisms behind BTI and noise that are difficult to obtain otherwise. Case studies relevant for practical applications and understanding of the basic mechanisms are presented and critically discussed.

Conductance-to-Current-Ratio-Based Parameter Extraction in MOS Leakage Current Models

A new procedure to extract the parameters of mathematical models that describe charge flow phenomena through thin dielectrics is proposed for characterizing undesirable leakage current mechanisms in modern MOSFETs’ gates. The procedure’s basis is the small signal conductance-to-current ratio of the $I$ – $V$ characteristics. It is an alternative to, and has advantages over, the other presently used methods that extract those models’ parameters from the slope and intercept of phenomenon-specific linear plots. In contrast, this is a generic method that may be directly applied to the $I$ – $V$ characteristics, regardless of the specific leakage mechanism involved. The procedure inherently reduces by one the number of unknowns that needs to be determined during numerical optimization. In addition, it does not require, as other traditional methods do, a prior knowledge of the exact relationship between the applied voltage and the effective internal electric field strength, which in this case is determined together with the other parameters. The procedure is illustrated by three examples with different kinds of data: mathematically synthesized, Computer Aided Design simulated, and experimentally measured leakage $I$ – $V$ characteristics of MOS capacitors.

Study of Timing Characteristics of NOT Gate Transistor Level Circuit Implemented Using Nano-MOSFET by Analyzing Sub-Band Potential Energy Profile and Current-Voltage Characteristic of Quasi-Ballistic Transport

This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.

An intelligent power MOSFET driver ASIC circuit with additional integrated safety operation functionality

This paper presents an extension to the previously presented conference paper [1] a power MOSFET driver ASIC with intelligent driving algorithm approach of the power modern MOSFET devices. The intelligent driving algorithm concept proposes a realization of power MOSFET gate driving with controlled source/sink current of the power MOSFET driver circuit. Such approach enables higher control of the power MOSFET operation behavior, especially during switching events. Additionally to the previously published work this paper presents implementation of the intelligent driving algorithm and driver safety operation functions on a single integrated ASIC circuit. The paper concludes with presentation of some functions of the manufactured ASIC circuit in CMOS technology.

Compact Modeling of Total Ionizing Dose and Aging Effects in MOS Technologies

This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I - V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.

Modeling the Impact of Multi-Fingering Microwave MOSFETs on the Source and Drain Resistances

Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent S-parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

Sub-threshold study of undoped trigate nFinFET

Modern MOSFET devices with undoped channel have a non-trivial current distribution, which is gate voltage dependent. In our work we have studied the sub-threshold behavior of undoped triple gate MOSFETs (FinFETs) using a thermionic transport model. We have analyzed the conductance data of such devices, and from this, we have been able to determine the evolution of both the active cross-section area of the channel and the barrier height as a function of the gate voltage. The result of our experiments shows good agreement with tight binding simulations and with analytical results. This confirms the validity of the use of our thermionic approach to study transport in sub-micrometer size FinFET devices and not only in micrometer size samples specially made for characterizations.

Modeling of modern MOSFETs with strain

We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22 nm technology node and beyond.

Modeling Techniques for Strained CMOS Technology

We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22nm technology node and beyond.

Modeling of Radiation-Induced Leakage and Low Dose-Rate Effects in Thick Edge Isolation of Modern MOSFETs

A procedure of SPICE parameters extraction for radiation-induced equivalent lumped parasitic transistor is proposed. Comparison of radiation-induced leakage current in test MOSFETs between total dose irradiation experiments and simulation results exhibits excellent agreement. Mathematical description of combined enhanced low dose-rate sensitivity and tunnel annealing effects as applied to the MOSFET subthreshold leakage has been developed. It has been numerically found that the ELDRS effects are significantly suppressed by the simultaneous tunnel annealing in the edge isolation of MOSFETs.

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Tunnelling field-effect transistors using graphene nanoribbons could significantly outperform modern MOSFETs

High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues

Compact modeling of the most important high-frequency (HF) noise sources of the MOSFET is presented in this paper, along with challenges in noise measurement and deembedding of future CMOS technologies. Several channel thermal noise models are reviewed and their ability to predict the channel noise of extremely small devices is discussed. The impact of technology scaling on noise performance of MOSFETs is also investigated by means of analytical expressions. It is shown that the gate tunneling current has a significant impact on MOSFETs noise parameters, especially at lower frequencies. Limitations of some commonly used noise models in predicting the HF noise parameters of modern MOSFETs are addressed and methods to alleviate some of the limitations are discussed

On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?

Continued success in scaling bulk MOSFETs has brought increasing focus on fundamental performance limits. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel. In this work, we show that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modern MOSFETs operate to the ballistic or "thermal limit." We propose a new technique and show that an advanced 1 V NMOS technology with L/sub eff/<50 nm operates at no more than /spl sim/40% of the limiting thermal velocity.

High frequency noise of MOSFETs. II. Experiments

In this paper, a set of scattering and noise measurements on devices fabricated in both 0.8 μm BiCMOS technology and a 0.35 μm CMOS technology were conducted to confirm the noise model proposed in ``High frequency noise of MOSFETs. I. Modeling'' [Chen, C. H. and Deen, M. J., Direct Calculation of the MOSFET High frequency noise Parameters, High frequency noise of MOSFETs. I. Modeling. Solid State Electronics, J. Vacuum Sci. Technol, 1998, 16(2), 850–854.]. Direct de-embedding techniques for obtaining the intrinsic scattering and noise parameters of devices were used and it is found that the probe pads with the geometry 60μm/50μm will increase the NF min of a 60μm/0.8μm n-type MOSFET by ∼0.5 dB. The accuracy of the probe pad model was confirmed by comparing the de-embedded noise parameters obtained by a direct de-embedding technique against those obtained using pad modeling. In addition, it was found experimentally that the induced gate noise is negligible in modern MOSFETs at high-frequencies. The gate resistance was demonstrated to have dramatic impact on the noise performance. By decreasing the gate resistance using multi-finger design, the noise performance improves. Finally, the excellent noise performance of state-of-the-art devices fabricated by using 0.35 μm CMOS technology with NF min=0.5 dB at 1 GHz is presented.