High frequency noise of MOSFETs. II. Experiments

Abstract

In this paper, a set of scattering and noise measurements on devices fabricated in both 0.8 μm BiCMOS technology and a 0.35 μm CMOS technology were conducted to confirm the noise model proposed in ``High frequency noise of MOSFETs. I. Modeling'' [Chen, C. H. and Deen, M. J., Direct Calculation of the MOSFET High frequency noise Parameters, High frequency noise of MOSFETs. I. Modeling. Solid State Electronics, J. Vacuum Sci. Technol, 1998, 16(2), 850–854.]. Direct de-embedding techniques for obtaining the intrinsic scattering and noise parameters of devices were used and it is found that the probe pads with the geometry 60μm/50μm will increase the NF min of a 60μm/0.8μm n-type MOSFET by ∼0.5 dB. The accuracy of the probe pad model was confirmed by comparing the de-embedded noise parameters obtained by a direct de-embedding technique against those obtained using pad modeling. In addition, it was found experimentally that the induced gate noise is negligible in modern MOSFETs at high-frequencies. The gate resistance was demonstrated to have dramatic impact on the noise performance. By decreasing the gate resistance using multi-finger design, the noise performance improves. Finally, the excellent noise performance of state-of-the-art devices fabricated by using 0.35 μm CMOS technology with NF min=0.5 dB at 1 GHz is presented.