Modern Field Programmable Gate Arrays Research Articles

Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers

The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.

Upgrade of ATLAS hadronic Tile Calorimeter for the High Luminosity LHC

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment. The High-Luminosity phase of LHC, delivering five times the LHC nominal instantaneous luminosity, is expected to start in 2029. TileCal will require new electronics to meet the requirements of a 1 MHz trigger, higher ambient radiation, and to ensure better performance under high pile-up conditions. Both the on- and off-detector TileCal electronics will be replaced during the shutdown of 2026–2028. Approximately 10% of the PMTs, those reading out the most exposed cells, will be replaced. PMT signals from every TileCal cell will be digitized and sent directly to the back-end electronics, where the signals are reconstructed, stored, and sent to the first level of trigger at a rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. The modular front-end electronics feature radiation-tolerant components and redundant design to minimise single points of failure. The timing, control and communication interface with the off-detector electronics is implemented with modern Field Programmable Gate Arrays (FPGAs) and high speed fiber optic links running up to 9.6 Gb/s. The TileCal upgrade program has included extensive R&D and test beam studies. A Demonstrator module equipped with the new electronics but with reverse compatibility with the existing readout system was inserted in ATLAS in 2019 for testing in actual detector conditions. The status of the various components and the results of test-beam campaigns with the electronics prototypes will be discussed.

Lookup Table Merging for FPGA Technology Mapping

Higher logic density is a key goal pursued by Field Programmable Gate Arrays (FPGA). The higher the logic density is, the lower the cost of the circuit spends, and the shorter the line length of the circuit is, the less power is required. Technology mapping is used to map technology-independent logic gates into a lookup table (LUT) netlist. A big problem with the 6-input LUT used in the FPAG at the present stage is that the utilization rate of the lookup table is insufficient. Modern FPGA architectures have good support for dual-output LUTs. We can merge two small LUTs into a new dual-output LUT, if the total number of inputs of the two small LUTs is not greater than the input limit specified by the LUT, thereby reducing the area, that is, reducing the number of LUTs. In this paper, the dual-output LUTs are merged in the technology mapping stage, and a new method of merging single-output LUTs into dual-output LUTs is proposed. The experimental results show that the algorithm used in this paper has an average reduction of 10.21 % in the number of LUTs without worsening delay.

Parameterized SDRAM-based content-addressable memory on field programmable gate array

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.

ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge

Partial reconfiguration (PR) is a key enabler to the design and development of adaptive systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs), allowing hardware to be adapted dynamically at runtime. Vendor-supported PR infrastructure is performance-limited and blocking, drivers entail complex memory management, and software/hardware design requires bespoke knowledge of the underlying hardware. This article presents ZyPR: a complete end-to-end framework that provides high-performance reconfiguration of hardware from within a software abstraction in the Linux userspace, automating the process of building PR applications with support for the Xilinx Zynq and Zynq UltraScale+ architectures, aimed at enabling non-expert application designers to leverage PR for edge applications. We compare ZyPR against traditional vendor tooling for PR management as well as recent open source tools that support PR under Linux. The framework provides a high-performance runtime along with low overhead for its provided abstractions. We introduce improvements to our previous work, increasing the provisioning throughput for PR bitstreams on the Zynq Ultrascale+ by 2× and 5.4× compared to Xilinx’s FPGA Manager.

Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities

Field-Programmable Gate Array (FPGA) is at the core of System on Chip (SoC) design across various Industry 5.0 digital systems—healthcare devices, farming equipment, autonomous vehicles and aerospace gear to name a few. Given that pre-silicon verification using Computer Aided Design (CAD) accounts for about 70% of the time and money spent on the design of modern digital systems, this paper summarizes the machine learning (ML)-oriented efforts in different FPGA CAD design steps. With the recent breakthrough of machine learning, FPGA CAD tasks—high-level synthesis (HLS), logic synthesis, placement and routing—are seeing a renewed interest in their respective decision-making steps. We focus on machine learning-based CAD tasks to suggest some pertinent research areas requiring more focus in CAD design. The development of open-source benchmarks optimized for an end-to-end machine learning experience, intra-FPGA optimization, domain-specific accelerators, lack of explainability and federated learning are the issues reviewed to identify important research spots requiring significant focus. The potential of the new cloud-based architectures to understand the application of the right ML algorithms in FPGA CAD decision-making steps is discussed, together with visualizing the scenario of incorporating more intelligence in the cloud platform, with the help of relatively newer technologies such as CAD as Adaptive OpenPlatform Service (CAOS). Altogether, this research explores several research opportunities linked with modern FPGA CAD flow design, which will serve as a single point of reference for modern FPGA CAD flow design.

Upgrade of ATLAS Hadronic Tile Calorimeter for the High Luminosity LHC

The Tile Calorimeter (TileCal) is a sampling hadron calorimeter covering the central region of the ATLAS experiment, with steel as absorber and plastic scintillators as active medium. The High Luminosity phase of the Large Hadron Collider (LHC) is expected to start in 2029 and five times the present instantaneous luminosity will be delivered by the machine. TileCal will require new electronics to meet the requirements of a 1 MHz trigger, to be robust against higher radiation level, and to ensure better performance under high pile-up conditions. Both the on- and off-detector TileCal electronics will be replaced during the shutdown of 2026-2028. PMT signals from every TileCal cell will be digitized and sent directly to the back-end electronics, where the signals are reconstructed, stored, and sent to the first level of trigger at a rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. The modular front-end electronics feature radiation-tolerant commercial off-the-shelf components and redundant design to minimise single points of failure. The timing, control and communication interface with the off-detector electronics is implemented with modern Field Programmable Gate Arrays and high speed fibre optic links running up to 9.6 Gb/s. The TileCal upgrade program has included extensive research and development studies, and test beam studies. A Demonstrator module with reverse compatibility with the existing system was inserted in ATLAS in August 2019 for testing in actual detector conditions. The ongoing developments for on- and off-detector systems, together with expected performance characteristics and results of test-beam campaigns with the electronics prototypes are discussed.

Designing Reconfigurable Cyber-Physical Systems Using Unified Modeling Language

Technological progress in recent years in the Cyber-Physical Systems (CPSs) area has given designers unprecedented possibilities and computational power, but as a consequence, the modeled CPSs are becoming increasingly complex, hierarchical, and concurrent. Therefore, new methods of CPSs design (especially using abstract modeling) are needed. The paper presents an approach to the CPS control part modeling using state machine diagrams from Unified Modelling Language (UML). The proposed design method attempts to combine the advantages of graphical notation (intuitiveness, convenience, readability) with the benefits of text specification languages (unambiguity, precision, versatility). The UML specification is transformed using Model-Driven Development (MDD) techniques into an effective program in Hardware Description Language (HDL), using Concurrent Finite State Machine (CFSM) as a temporary model. The obtained HDL specification can be analyzed, validated, synthesized, and finally implemented in Field Programmable Gate Array (FPGA) devices. The dynamic, partial reconfiguration (a feature of modern FPGAs) allows for the exchange of a part of the implemented CPS algorithm without stopping the device. But to use this feature, the model must be safe, which in the proposed approach means, that it should possess special idle states, where the control is transferred during the reconfiguration process. Applying the CFSM model greatly facilitates this task. The proposed design method offers efficient graphical modeling of a control part of CPS, and automatic translation of the behavior model into a synthesizable Verilog description, which can be directly implemented in FPGA devices, and dynamically reconfigured as needed. A practical example illustrating the successive stages of the proposed method is also presented.

Accelerating legacy applications with spatial computing devices

Heterogeneous computing is the major driving factor in designing new energy-efficient high-performance computing systems. Despite the broad adoption of GPUs and other specialized architectures, the interest in spatial architectures like field-programmable gate arrays (FPGAs) has grown. While combining high performance, low power consumption and high adaptability constitute an advantage, these devices still suffer from a weak software ecosystem, which forces application developers to use tools requiring deep knowledge of the underlying system, often leaving legacy code (e.g., Fortran applications) unsupported. By realizing this, we describe a methodology for porting Fortran (legacy) code on modern FPGA architectures, with the target of preserving performance/power ratios. Aimed as an experience report, we considered an industrial computational fluid dynamics application to demonstrate that our methodology produces synthesizable OpenCL codes targeting Intel Arria10 and Stratix10 devices. Although performance gain is not far beyond that of the original CPU code (we obtained a relative speedup of times 0.59 and times 0.63, respectively, for a single optimized main kernel, while only on the Stratix10 we achieved times 2.56 by replicating the main optimized kernel 4 times), our results are quite encouraging to drawn the path for further investigations. This paper also reports some major criticalities in porting Fortran code on FPGA architectures.

Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA

Due to technological advancements and voltage scaling, leakage power has become an important concern in CMOS design. The implementation of a field-programmable gate array (FPGA) circuit utilizes a portion of the FPGA’s resources as compared to an application-specific integrated circuit (ASIC). Both the utilized and unutilized parts of the FPGA dissipate leakage power. In this work, two dynamic power gating techniques, PSG-1 and PSG-2, are proposed, which are able to reduce the leakage power of the 6-input look-up table (LUT) used in the Xilinx Spartan-6 series. The obtained results show that the proposed approaches PSG-1 and PSG-2 reduce average leakage power by 54.61% and 66.69%, respectively, at the expense of nominal area and delay overhead. The proposed method is also capable of lowering the average total power of the 6-input LUT. The suggested PSG-1 and PSG-2 approaches reduce average power by 53.75% and 60.83%, respectively. However, header-based power supply gating is extremely vulnerable to the negative-bias temperature instability (NBTI) aging effect and, due to this, the lifetime of the circuit is reduced considerably. Therefore, in this work, lifetime estimation-based analysis is performed by varying the stress probability of the sleep transistor. The results show that the LUT with PSG-1 and PSG-2 techniques has a lifetime of 4.55 years and 11.13 years, respectively. The stress time of the sleep transistor is 50% for the PSG-1 technique and 25% for the PSG-2 technique, respectively.

Upgrade of ATLAS Hadronic Tile Calorimeter for the High-Luminosity LHC

The Tile Calorimeter (TileCal) is a sampling hadronic calorimeter covering the central region of the ATLAS experiment, with steel as the absorber and plastic scintillators as the active medium. The High-Luminosity phase of the LHC, delivering five times the LHC’s nominal instantaneous luminosity, is expected to begin in 2029. TileCal will require new electronics to meet the requirements of a 1 MHz trigger, higher ambient radiation, and to ensure better performance under high pile-up conditions. Both the on- and off-detector TileCal electronics will be replaced during the shut-down of 2026–2028. The photomultiplier tube (PMT) signals from every TileCal cell will be digitized and sent directly to the back-end electronics, where the signals are reconstructed, stored, and sent to the first level of the trigger at a rate of 40 MHz. This will provide better precision in the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. The modular front-end electronics feature radiation-tolerant, commercial, off-the-shelf components and a redundant design to maintain system performance in case of single points of failure. The timing, control, and communication interface with the off-detector electronics is implemented with modern Field-Programmable Gate Arrays (FPGAs) and high-speed fiber optic links running up to 9.6 Gb/s. The TileCal upgrade program has included extensive R&D and test beam studies. A Demonstrator module with reverse compatibility with respect to the existing system was inserted in ATLAS in August 2019 for testing in actual detector conditions. The ongoing developments for on- and off-detector systems, together with expected performance characteristics and results of test-beam campaigns with the electronics prototypes, will be discussed.

An Incremental Placement Flow for Advanced FPGAs With Timing Awareness

As interconnects dominate circuit performance in modern field programmable gate arrays (FPGAs), placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints and, thus, may lead to illegal routing solutions. In this article, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves a 5.1% improvement in worst slack and produce placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking

Both modern datacenter and embedded Field Programmable Gate Arrays (FPGAs) provide great opportunities for high-performance and high-energy-efficiency computing. With the growing public availability of FPGAs from major cloud service providers such as AWS, Alibaba, and Nimbix, as well as uniform hardware accelerator development tools (such as Xilinx Vitis and Intel oneAPI) for software programmers, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS). The major goal of this article is to figure out how to efficiently access the memory system of modern datacenter and embedded FPGAs in HLS-based accelerator designs. This is especially important for memory-bound applications; for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including (1) the clock frequency of the accelerator design, (2) the number of concurrent memory access ports, (3) the data width of each port, (4) the maximum burst access length for each port, and (5) the size of consecutive data accesses. Then, we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the memory systems of datacenter FPGAs (Xilinx Alveo U200 and U280) and embedded FPGA (Xilinx ZCU104) when changing those affecting factors, and we provide insights into efficient memory access in HLS-based accelerator designs. Comparing between the typically used soft and hardened memory systems, respectively, found on datacenter and embedded FPGAs, we further summarize their unique features and discuss the effective approaches to leverage these systems. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms on datacenter FPGAs with a soft (and thus more flexible) memory system. Compared to the baseline designs, optimized designs leveraging our insights achieve about \( 3.5\times \) and \( 8.5\times \) speedups for the KNN and SpMV accelerators. Our final optimized KNN and SpMV designs on a Xilinx Alveo U200 FPGA fully utilize its off-chip memory bandwidth, and achieve about \( 5.6\times \) and \( 3.4\times \) speedups over the 24-core CPU implementations.

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs

Field-programmable gate arrays (FPGAs) having software-like reconfigurability and hardware-like performance are adopted as developing platforms to implement complex systems, i.e., software-defined networks (SDNs). Ternary content-addressable memory (TCAM) is not present in modern FPGA, but rather it is used as a softcore where needed. The hardware structure of an FPGA is flexible but rigid; the elemental structure is fixed and can be used in a limited number of ways. Existing FPGA-based TCAMs exhaust one particular type of memory when a large size is implemented, resulting in a shortage of memory for the rest of the system. Our proposed architecture uses only those memory elements of FPGA that are redundant and not used by other parts. In this letter, the proposed architecture, comp-TCAM, combines both block RAM (BRAM) and lookup table RAM (LUTRAM) to implement the TCAM architecture; that eliminates the dependency on the type of memory and is adaptable to the requirement of the system. Evaluation results show the feasibility, scalability, and effectiveness of the proposed TCAM architecture compared to the existing TCAM architectures. The hardware resource utilization on Xilinx VIrtex-7 FPGA is reduced by 41.6% compared to state-of-the-art FPGA-based TCAM with no harm to the system’s performance providing a throughput of 21.06 Gbits/s.

FPGA Accelerated Post-Quantum Cryptography

Recent advancement in quantum information processing technology has led to the emergence of advanced cryptography in the post-quantum era. Next generation cryptographic techniques aim to be mathematically resistant against any known attacks related to quantum computing, and can be easily implemented on traditional hardware platforms. The National Institutes of Standards and Technology (NIST) has entered the fourth-round standardization process of post-quantum cryptography (PQC). Software implementations of PQC candidates have been widely investigated. Interests in domain-specific hardware acceleration of PQC algorithms have risen, in particular using field-programmable gate arrays (FPGAs). While conventional general-purpose hardware platforms have been used for PQC implementations, modern FPGAs promise software-hardware co-optimisation, deep pipeline parallelism and trivial support for custom-precision arithmetic. Therefore, the time is ripe for reviewing recent FPGA-based PQC implementations. This article first surveys state-of-the-art advances in PQC implementations on FPGAs, including fast arithmetic, algorithm-hardware codesign approaches and open-source PQC hardware projects, then gives a brief review of recent attacks on PQC algorithms and their hardware implementations. Finally, we summarise the challenges for hardware implementations along with potential research directions in this promising field.

A Timing, Trigger, and Control System With Picosecond Precision Based on 10 Gbit/s Passive Optical Networks for High-Energy Physics

The Large Hadron Collider (LHC) experiments will have their timing, trigger, and control (TTC) system upgraded as a consequence of the need for higher bandwidth and components which are obsolete. In this article, we present a TTC based on passive optical networks (PONs). TTC-PON is a point-to-multipoint bidirectional TTC system based on the 10 Gbit/s International Telecommunications Union (ITU) XG-PON technology and modern field-programmable gate array (FPGA) devices. Each master can handle up to 64 slaves through a fully passive network, delivering a fixed-phase recovered clock to all the destinations with less than 5-ps jitter. TTC-PON pushes the limits of the PON technology by exploiting cutting-edge custom protocols on top of the commercially available XG-PON optical modules. It can potentially reuse the current optical fiber infrastructure already installed in the experiments and allows for high flexibility in terms of partitioning, which can ease future upgrades of the TTC network. The system features a picosecond-level on-the-fly phase monitoring for each slave's recovered clock by exploiting the bidirectionality of the network. In addition, a full set of link-quality monitoring tools was developed, allowing real-time performance monitoring. An overview of the tailored protocols will be given together with the details on the system implementation, operation, and performance. A discussion on the characterization campaign of more than 1000 optical modules delivered to the first implementation of the TTC-PON system will be drawn.

A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks

The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit-by-digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie-Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA-based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature.

Introduction Of Special Issue on FPGA-Based Computing [From The Guest Editors

The articles in this special section focus on field-programmable gate arrays (FPGAs)- based computing. Over the past three decades, FPGAs have evolved from small chips with a few thousand logic blocks to billion- transistor system-on-chips. Modern FPGAs provide massive fine-grained parallelism, high energy efficiency, and more predictable performance than CPUs and GPUs. More importantly, they can be reconfigured to implement a special-purpose architecture that is specifically customized based on the key characteristics of a target application (or domain). For these reasons, recent years have seen a rapidly increasing use of FPGAs for computing, where a plethora of new architectures, compilers, and FPGA-accelerated applications are being demonstrated and actively developed. This special issue includes five survey papers from renowned experts in the field of FPGAs. The goal is to summarize some of the recent advances on FPGA-based computing, to elucidate the architecture- and application-level trends, and to promote new tools to enable productive FPGA programming.

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

The increasing size of modern field programmable gate arrays (FPGAs) allows for ever more complex applications to be mapped onto them. However, long design implementation times for large designs can severely affect design productivity. A modular design methodology can improve design productivity in a divide and conqueror fashion but at the expense of degraded performance and power consumption of the resulting implementation. To reduce the dominant power dissipation component in FPGAs, the routing power, methodologies have been proposed that consider data communication between modules during module formation and placement on the FPGA. Selecting proper mapping region on target FPGAs, on the other hand, is becoming a critical process because of the heterogeneous resources and column arrangements in modern FPGAs. Selecting inappropriate FPGA regions for mapping could lead to degraded performance. Hence, we propose a methodology that uses communication-aware module placement, such that modules are mapped by selecting the best shape and region on the FPGA factoring the columnar resource arrangements. Additionally, techniques for module locking and splitting have been proposed for deterministic convergence of the algorithm and for improved module placement. This methodology exhibits nearly 19% routing power reduction with respect to commercial CAD flows without any degradation in achievable performance.