Threshold Voltage Model Research Articles

Drain-induced barrier-lowering effect in surrounding-gate schottky barrier metal-oxide semiconductor field transistor

Based on surrounding-gate schottky barrier metal-oxide semiconductor field transistor (MOSFET) structure, the distribution of surface potential is obtained by solving two-dimensional Poisson equation in cylindrical coordinates, and the threshold voltage model of surrounding-gate schottky barrier NMOSFET which is applicable to the low voltage of drain is built. According to the calculation results, the dependences of threshold voltage and drain-induced barrier-lowering on voltage of drain, channel radius and channel length are studied in detail, which can provide some reference for the design of surrounding-gate schottky barrier MOSFET device and circuit.

Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

Physical compact modeling for threshold voltage of strained Si NMOSFET

The development of strained-Si physical compact threshold voltage model is based on Poisson's equation, using the gradual channel approximation (GCA) and coherent quasi-two-dimensional (2D) analysis, as well as taking into account the effects of short channel effect (SCE), narrow channel effect (NCE), non-uniform doping effect, and drain-induced barrier lowering (DIBL) effect. Moreover, the threshold voltage parameters are extracted from the experimental results by software. Finally, the validity of our model is derived from the comparison of our simulation results. The proposed model may be useful for the design and simulation of very large scale integrated circuits (VLSI) made of strained-Si.

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the "virtual cathode" concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1?x Ge x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.

A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs

Based on the quasi-2-D scaling equation, a new threshold voltage model for short-channel junctionless (JL) cylindrical surrounding gate (JLCSG) MOSFETs is developed. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage behavior. The model can also be extendable to its counterpart of junction-based cylindrical surrounding gate (JBCSG) MOSFETs. The model is verified by its calculated results matching well with those of the 3-D numerical simulator and can be easily used to explore the threshold voltage characteristics of JLCSG MOSFETs for its simple formula and computational efficiency.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (VT) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (@fs) to a value @fsT necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that @fsT. The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3x10^1^5-5x10^1^7/cm^3. Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature.

Simple and Efficient MASTAR Threshold Voltage and Subthreshold Slope Models for Low-Doped Double-Gate MOSFET

In this brief, we propose simple and analytical models for threshold voltage and subthreshold slope including short-channel and quantum effects for fully depleted or undoped double-gate MOS devices.

A Quasi-Two-Dimensional Threshold Voltage Model for Short-Channel Junctionless Double-Gate MOSFETs

Based on the bulk conduction mode of the quasi-2-D scaling theory, an analytical threshold voltage model for short-channel junctionless (JL) double-gate MOSFETs is developed for the first time. The model explicitly shows how the device parameters such as the silicon thickness, oxide thickness, drain bias, and channel length affect the threshold voltage degradation. The model can also be extended to modeling accumulation/inversion operation mode for JL/junction-based double-gate MOSFETs. The model is verified by 2-D device simulations and can be easily used to explore the threshold voltage behavior of the JL double-gate MOSFETs due to its simple formula and computational efficiency.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm–5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (Vth) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φc) saturates to Φc(sat), and analyze the effects of oxide thickness (tox) and substrate doping (NA) variations on Vth. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed Vth definition, electrically corresponds to a condition where the inversion layer capacitance (Cinv) is equal to the oxide capacitance (Cox) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria Cinv=Cox is proposed to compute Φc(sat), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (“x”) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film.

The potential of Fe-FET for robust design under variations: A compact modeling study

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization–electrical field (P–E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper, a new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET. It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.

High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.

A Novel Short-Channel Model for Threshold Voltage of Trigate MOSFETs With Localized Trapped Charges

Based on the scaling equation and perimeter-weighted-sum approach, a novel short-channel threshold voltage model for the trigate (TG) MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flatband voltage. The model shows how the positive/negative trapped charges, silicon thickness, silicon width, oxide thickness, and normalized damaged zone affect the threshold voltage behavior. The model is verified by the 3-D device simulator “DESSIS” and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced TG charge-trapped memory device.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.

Two Dimensional Analytical Threshold Voltage Model of Nanoscale Strained Si/Si<SUB>1–<I>x</I></SUB> Ge<SUB><I>x</I></SUB> MOSFETs Including Quantum Mechanical Effects

A new analytical model derived from the Poisson equation for surface potential and threshold voltage (V th), including the Quantum Mechanical Effects (QMEs) is presented for nanoscale strained Si1–x Ge x MOSFETs. Boundary condition approaches are applied in the model. The threshold voltage analytical model is developed using 20% germanium content in Si1–x Ge x substrates. The model is developed to investigate the quantum mechanical effects on the magnitude of surface potential and threshold voltage. The impacts of strain and quantum confinement on the shift of threshold voltage are explained. Our threshold voltage model incorporates the quantum oxide thickness and the effective flatband voltage. For the validation purpose, the developed threshold model is verified using 2D ATLAS simulation results. The results obtained from the developed model have a good agreement with the simulation results. Both the analytical and the simulation results demonstrate a significant increase of threshold voltage in strained silicon considering the quantum mechanical effects.

Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor

Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor

Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor

In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors.

Study of gate depletion effect in strained Si NMOSFET with polycrystalline silicon germanium gate

Based on the analysis of Poly-Si1-xGex gate work function and by solving Poisson equation, the models of vertical electric field and potential distribution in strained Si NMOSFET with Poly-Si1-xGex gate are obtained; threshold voltage model and the gate depletion thickness and it's normalization model are established in strained Si NMOSFET based on the above results, with the gate depletion effect of Poly-Si1-xGex taken into account. Then the influences of device geometrical and physical parameters of device especially the Ge fraction on Poly-Si1-xGex gate depletion thickness are investigated. Furthermore, the effect of gate depletion thickness on threshold voltage is analyzed. It shows that the poly depletion thickness decreases with the increases of Ge fraction and gate doping concentration, while it increases with the increase of substrate doping concentration. Furthermore, the threshold voltage increases with the increase of gate depletion thickness. The results can provide theoretical references to the design of strained Si devices.

A analytic model for the threshold-voltage of novel high-speed semiconductor device IMOS

A threshold voltage model is created by analyzing differents distributions of surface electric field and the condition of avalanche breakdown, based on the structure of a novel high speed semiconductor device p-IMOS in this paper. Model verification is carried out using the 2D device simulator ISE. By analyzing the model, the dependences of threshold voltage on drain-source voltage, Si layer thickness and gate length are studied. The results of the model are in good agreement with experimental results and ISE simulation results. The proposed model can also be easily used for the reasonable analysis and the design of p-IMOS.

Threshold-voltage and hole-sheet-density model of quantum well Si/SiGe/Si p field effect transistor

The low hole mobility restricts the application of Si complementary metal-oxide-semiconductor in high frequency fields. In this paper, the SiGe p-metal-oxide-semiconductor field-effect-transistor (PMOSFET) is studied. By numeric modeling and analysis, the vertical potential distribution of the device is obtained through solving one-dimensional Poisson equations, and the threshold-voltage model is established. The effects of Ge-profile, thickness of Si buffer layer, thickness of Si cap layer and substrate doping on the threshold-voltage are discussed. In SiGe layer, the quantization effect of the potential well in valence band is taken into account. When the gate voltage is large enough, the holes in SiGe channel layer will transit to the Si/SiO2 interface due to band bending and energy level splitting, causing the degradation of device performance. Thus, the hole-sheet-density model in quantum channel of SiGe PMOSFET is established, and the concept of the maximum operating gate voltage is proposed, moreover the channel saturation induced by gate voltage is calculated and analyzed. The results show that the threshold voltage and the maximal operating gate voltage are related to Ge-profile, and a proper increase of Ge-profile can extend the range of the operating gate voltage effectively.

Analytical V TH and S models for (DMG–GC–stack) surrounding-gate MOSFET

This article presents an analytical model of surface potential, threshold voltage and subthreshold swing for a new structure of surrounding-gate MOSFET by combining dual-material gate, graded channel and gate stack. By comparison with published results, it is shown that the new MOSFET structure can improve the immunity of CMOS-based devices in the nanoscale regime against short-channel effects.