Hot-carrier Degradation Model Research Articles

Characterization and Modeling of Hot Carrier Degradation Under Dynamic Operation Voltage

Characterization and Modeling of Hot Carrier Degradation Under Dynamic Operation Voltage

Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range.

We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

An Analytical Model of Hot Carrier Degradation in LDMOS Transistors: Rediscovery of Universal Scaling

It is well-known that regardless of the voltage/temperature/device structure, the hot carrier degradation (HCD) of classical logic transistors scales onto a single universal curve, offering a theory-agnostic approach to predict long-term degradation based on short-term accelerated tests. Based on the experimental results, it has been suggested that the HCD in power transistors [e.g., laterally diffused MOS (LDMOS)] is structurally and functionally so fundamentally different that an analogous universal scaling cannot apply. This article uses a tandem FET (two MOS) model of an LDMOS to explore the physical origin of the anomalous HCD degradation in power transistors and establish the general principle needed to restore the universality of the degradation kinetics. Interestingly, the empirical models used to evaluate HCD degradation in power transistors emerge naturally as approximations of the generalized approach. This article establishes the fact that the physics of HCD is universal and provides an example of nonclassical but predictive degradation in power transistors. This takes us a step closer to a generalized HCD model encompassing all the devices, including logic, memory, and power transistors.

A unified aging compact model for hot carrier degradation under mixed-mode and reverse E-B stress in complementary SiGe HBTs

This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction–diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions. The model accuracy has been validated against results from long-term aging tests performed close to the safe-operating-areas of an advanced complementary 0.25 µm BiCMOS technology. Degradation asymmetry observed between NPN and PNP devices is accurately captured by this unified aging compact model. This study highlights the challenges of predicting degradation of complementary circuits and thereby improving its functionalities by designing better-matched NPN and PNP HBTs.

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach.

We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.

Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs

In this article, we present a detailed analysis of the dependence of hot-carrier (HC) induced damage on the device design parameters in silicon-on-insulator (SOI) gate-all-around (GAA) nanowire (NW) n-field-effect transistors (FETs). Particularly, the HC reliability of NWs at extremely small (5 nm) to large (40 nm) widths is assessed for devices with different gate lengths. A substantial improvement in device reliability is observed at smaller NW widths, which could be due to the quantization effects and reduced effective stress voltages due to the increase in source/drain resistance. The difference in prestress device parameters, such as threshold voltage and source/drain resistance, is shown to affect the HC degradation (HCD) by altering the actual stress voltages applied to the device. Further, the impact of self-heating on the HCD mechanism is studied for devices with different fin density and gates per active region. Consequently, an empirical model is extracted using the measurement results where the empirical prefactors accurately capture the degradation in deeply scaled GAA-NWFETs.

A physical and versatile aging compact model for hot carrier degradation in SiGe HBTs under dynamic operating conditions

This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick’s law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.

Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias on self-heating (SH) enhanced hot-carrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias. The influence of SH on electrical parameter degradation due to hot-carriers is shown as an important metric for accurate device reliability analysis. The relative contribution of bulk and interface traps is determined to identify the dominant mechanism responsible for HCD for different device geometries. The device behavior is thoroughly studied under hot-carrier DC and AC stresses for different device design parameters, such as effective oxide thickness, number of fins, and channel length. Based on measured data, we have proposed an empirical model for reliability degradation, which takes into account some of the key device design parameters and stress bias frequency.

Effects of hot-carrier degradation on the low frequency noise in strained-Si p-MOSFETs

The aim of this work is to study hot carrier degradation starting from microscopic mechanisms of defect generation and its effects on noise behaviour of scaled strained-Si MOSFETs. As device dimensions decrease, hot carrier effects, which are mainly due to the presence of a high electric field inside the device, are becoming a major device/circuit design concern. Studies of hot carrier degradation in high-mobility SiGe channel MOSFETs, in which a more severe degradation is expected due to the smaller bandgap compared to Si, are highly essential. A comprehensive model for hot carrier degradation has been used in simulation to capture the physical picture behind these detrimental effects. In this work, hot carrier degradation modelling issues have been carefully analysed and a comprehensive physics-based hot carrier degradation simulation study has been taken up. Peculiarities of the defect generation kinetics as well as their impact on degradation are discussed. We present the results of our studies on the hot carrier degradation in novel high-mobility SiGe/strained-Si channel MOSFETs and its effects on the low-frequency noise. It is shown due to hot carrier degradation, the hole mobility is degraded by about 40% after stressing. A two-fold degradation in drain current is also observed.

Effects of hot-carrier degradation on the low frequency noise in strained-Si p-MOSFETs

The aim of this work is to study hot carrier degradation starting from microscopic mechanisms of defect generation and its effects on noise behaviour of scaled strained-Si MOSFETs. As device dimensions decrease, hot carrier effects, which are mainly due to the presence of a high electric field inside the device, are becoming a major device/circuit design concern. Studies of hot carrier degradation in high-mobility SiGe channel MOSFETs, in which a more severe degradation is expected due to the smaller bandgap compared to Si, are highly essential. A comprehensive model for hot carrier degradation has been used in simulation to capture the physical picture behind these detrimental effects. In this work, hot carrier degradation modelling issues have been carefully analysed and a comprehensive physics-based hot carrier degradation simulation study has been taken up. Peculiarities of the defect generation kinetics as well as their impact on degradation are discussed. We present the results of our studies on the hot carrier degradation in novel high-mobility SiGe/strained-Si channel MOSFETs and its effects on the low-frequency noise. It is shown due to hot carrier degradation, the hole mobility is degraded by about 40% after stressing. A two-fold degradation in drain current is also observed.

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.

Hot-Carrier Degradation Modeling of Decananometer nMOSFETs Using the Drift-Diffusion Approach

We extend our previously suggested drift-diffusion (DD)-based hot-carrier degradation model to the case of decananometer transistors. Special attention is paid to the effect of electron-electron scattering, which populates the high energy tail of the carrier distribution function, by using a rate balance equation. We compare the results of the DD-based model with the results obtained from a spherical harmonics expansion of the Boltzmann transport equation as well as experimental data. We also study the accuracy and limits of the applicability of the DD-based model and conclude that this model is able to capture hot-carrier degradation in nMOSFETs over a range of gate lengths from 65 to 300 nm with excellent accuracy.

On the limits of applicability of drift-diffusion based hot carrier degradation modeling

We study the limits of the applicability of a drift-diffusion (DD) based model for hot-carrier degradation (HCD). In this approach the rigorous but computationally expensive solution of the Boltzmann transport equation is replaced by an analytic expression for the carrier energy distribution function. On the one hand, we already showed that the simplified version of our HCD model is quite successful for LDMOS devices. On the other hand, hot carrier degradation models based on the drift-diffusion and energy transport schemes were shown to fail for planar MOSFETs with gate lengths of 0.5–2.0 µm. To investigate the limits of validity of the DD-based HCD model, we use planar nMOSFETs of an identical topology but with different gate lengths of 2.0, 1.5, and 1.0 µm. We show that, although the model is able to adequately represent the linear and saturation drain current changes in the 2.0 µm transistor, it starts to fail for gate lengths shorter than 1.5 µm and becomes completely inadequate for the 1.0 µm device.

Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs

Using our physics-based model for hot-carrier degradation (HCD), we analyze the temperature behavior of HCD in nMOSFETs with a channel length of 44 nm. It was observed that, contrary to most previous findings, the linear drain current change ( $\Delta I_{\mathrm {d,lin}} $ ) measured during hot-carrier stress in these devices appears to be lower at higher temperatures. However, the difference between the $\Delta I_{\mathrm {d,lin}} $ values obtained at different temperatures decreases as the stress voltage increases. This trend is attributed to the single-carrier process of Si–H bond rupture, which is enhanced by the electron–electron scattering. We also consider another important modeling aspect, namely, the vibrational life-time of the Si–H bond, which also depends on the temperature. We finally show that our HCD model can successfully capture the temperature behavior of HCD with physically reasonable parameters.

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.

The role of cold carriers and the multiple-carrier process of Si–H bond dissociation for hot-carrier degradation in n- and p-channel LDMOS devices

We apply our hot-carrier degradation (HCD) model, which uses the information about the carrier energy distribution, to represent HCD data measured in n- and p-channel LDMOS transistors. In the first version of our model we use the spherical harmonics expansion approach to solve the Boltzmann transport equation (BTE), while in the second version we employ the drift–diffusion scheme. In the latter case the carrier energy distribution function is approximated by an analytic expression with parameters found using the drift–diffusion scheme. The model, which has already been verified with nLDMOS transistors, is used to represent the carrier distribution functions, interface state density profiles, and changes of the drain currents vs. stress time in pLDMOS transistor. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. We check the validity of the model by neglecting the effect of cold carriers in HCD modeling in the case of nLDMOS devices stressed at high voltages. In our model, cold carriers are represented by the corresponding term in the analytic formula for the carrier distribution function as well as by the multiple-carrier process of the Si–H bond dissociation. We show that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

Comparison of analytic distribution function models for hot-carrier degradation modeling in nLDMOSFETs

We analyze the applicability of different analytic models for the carrier distribution function (DF), namely the heated Maxwellian, the Cassi model, the Hasnat approach, the Reggiani model, and our own concept, to describe hot-carrier degradation (HCD) in nLDMOS devices. As a reference, we also obtain the carrier distribution function as a direct solution of the Boltzmann transport equation using the spherical harmonics expansion method. The DFs evaluated with these models are used to simulate the interface state generation rates, the interface state density profiles, and changes of the linear and saturation drain currents as well as the threshold voltage shift. We show that the heated Maxwellian approach leads to an underestimated HCD at long stress times. This trend is also typical for the Cassi and Hasnat models but in these models HCD is underestimated in the entire stress time window. While the Reggiani model gives good results in the channel and drift regions, it cannot properly represent the high-energy tails of the DF near the drain, and thus leads to a weaker curvature of the degradation traces. We show finally that our model is capable of capturing DFs with very good accuracy and, as a result, the change of the device characteristics with stress time.

Modeling of Hot-Carrier Degradation in nLDMOS Devices: Different Approaches to the Solution of the Boltzmann Transport Equation

We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.