Model For Double-gate MOSFETs Research Articles

An optimized nanoscale Quasi-Ballistic DG MOSFET model with diffusive carrier scattering dependency

ABSTRACT The work proposes a physically accurate quasi-ballistic drain current model valid for Double Gate (DG) MOSFETs in the nanoscale regime. The proposed quasi-ballistic model considers the carrier scattering physics and includes both ballistic and diffusive transport. Based on the concepts of scattering theory, a semi-empirical approach is used to determine the diffusive carrier scattering at the critical channel length as a function of drain bias. A generalised three region scale length model is applied to the proposed device structure with arbitrary dielectric constants and oxide thicknesses to examine the device channel length scaling limits. The significance of Eigen values and the scale length equations applicable for the proposed device structure is discussed. The drain current model essentially captures the key signature effect observed in rigorously scaled short channel devices. Further, the proposed quasi-ballistic model demonstrates its physical aptness and optimal accuracy when compared with other similar recent works. The model results obtained are verified using numerical simulations and are found to exhibit excellent continuity in all regions of the device operation.

Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits

Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits

Modeling of DG MOSFET <inline-formula> <tex-math notation="LaTeX">$I$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">$V$ </tex-math> </inline-formula> Characteristics in the Saturation Region

A double-gate MOSFET model that goes beyond the gradual channel approximation is developed by incorporating the effect of lateral field gradient on carrier density. It is shown that while the oxide field crosses zero at the point of saturation and becomes negative beyond it, the channel is not pinched off of charge carriers. The model generates $\text {I}_{\text {ds}}$ – $\text {V}_{\text {ds}}$ characteristics continuous into the saturation region with the finite output conductance consistent with TCAD. An explicit expression is derived for the output conductance in saturation in terms of basic device parameters.

A quantum wave based compact modeling approach for the current in ultra-short DG MOSFETs suitable for rapid multi-scale simulations

Source-to-drain (SD) tunneling decreases the device performance in MOSFETs falling below the 10nm channel length. Modeling quantum mechanical effects including SD tunneling has gained more importance specially for compact model developers. The non-equilibrium Green’s function (NEGF) has become a state-of-the-art method for nano-scaled device simulation in the past years. In the sense of a multi-scale simulation approach it is necessary to bridge the gap between compact models with their fast and efficient calculation of the device current, and numerical device models which consider quantum effects of nano-scaled devices. In this work, an NEGF based analytical model for nano-scaled double-gate (DG) MOSFETs is introduced. The model consists of a closed-form potential solution of a classical compact model and a 1D NEGF formalism for calculating the device current, taking into account quantum mechanical effects. The potential calculation omits the iterative coupling and allows the straightforward current calculation. The model is based on a ballistic NEGF approach whereby backscattering effects are considered as second order effect in a closed-form. The accuracy and scalability of the non-iterative DG MOSFET model is inspected in comparison with numerical NanoMOS TCAD data for various channel lengths. With the help of this model investigations on short-channel and temperature effects are performed.

Analytical Modeling of DG-MOSFET in Subthreshold Regime by Green’s Function Approach

In this paper, we have developed an analytical model of double gate MOSFET using Green's function approach in the subthreshold regime of operation. The exact analytical solution to 2-D Poisson's equation by Green's function approach is redefined and Fourier coefficients are calculated correctly that has a direct impact on the outcomes of the model. The approach considers 2-D mixed boundary conditions and multizone techniques while deriving potential equations. It is observed that the Green's function approach of solving 2-D Poisson's equation in both oxide and silicon region can accurately predict channel potential, subthreshold current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ), and subthreshold slope of both long and short channel devices designed with higher as well as lower t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">si</sub> /t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> oxide thickness ratio.

A Unified Continuous and Discrete Model for Double-Gate MOSFETs With Spatially Varying or Pulsed Doping Profiles

This paper presents a unified continuous and discrete model covering all device operating regions of double-gate MOSFETs for the first time. With a specific variable transformation method, the 1-D Poisson’s equation in the Cartesian coordinate for double-gate MOSFETs is transformed into the corresponding form in the cylindrical coordinate. Such a transformed cylindrical Poisson’s equation results in a simple algebraic equation, which correlates the (inversion-charge induced) surface potential to the field and allows the long-channel drain-current formula to be derived from the Pao–Sah integral. This model can be readily applied to predict the effects of both continuous and discrete doping variations. The short-channel-effect model is also developed by solving the 2-D Poisson’s equation using the eigenfunction-expansion method. The accuracy of both long-channel and short-channel models is confirmed by the numerical calculations and TCAD simulations.

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results.

Drain current model of double-gate MOSFETs considering both electrons and holes

We present a rigorously derived current solution for undoped double-gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third-order Newton–Raphson (NR) method is used to solve the surface-potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface-potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10−15. The drain current model for two carriers is presented as a benchmark to test the accuracy of one-carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

Surface Potential Based Analytical Modeling of Double Gate MOSFET with Si and Au Nano-Dots Embedded Gate Dielectric for Non-Volatile Memory Applications

In this paper we present an analytical study of Double Gate (DG) MOSFET memory devices with Si and Au nanocrystal embedded gate dielectric stacks. We considered an undoped long channel DG MOSFET, having a multilayer SiO2 (5 nm)–Si/Au nc embedded Si3N4 (6 nm)–SiO2 (7 nm) gate dielectric. From a quasi-1-D analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter following a trap-like model using the WKB approximation, we have investigated the Fowler Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. We evaluated the write-erase characteristics, gate tunneling currents, threshold voltage shifts and the output characteristics of the NVM devices from our analytical model. The performance of the nanoparticle embedded DGMOS memory device was compared with that of a DG SONOS NVM of similar dimensions. From the studies, the nc embedded devices showed better performance than the conventional SONOS DGMOS NVM. Among the two ncs compared the nc-Au embedded device emerged as the better performer in terms of higher charge density, faster charging, higher threshold voltage shift and better charge retention.

In-depth analysis and modelling of self-heating effects in nanometric DGMOSFETs

Self-heating effects (SHEs) in nanometric symmetrical double-gate MOSFETs (DGMOSFETs) have been analysed. An equivalent thermal circuit for the transistors has been developed to characterise thermal effects, where the temperature and thickness dependency of the thermal conductivity of the silicon and oxide layers within the devices has been included. The equivalent thermal circuit is consistent with simulations using a commercial technology computer-aided design (TCAD) tool (Sentaurus by Synopsys).In addition, a model for DGMOSFETs has been developed where SHEs have been considered in detail, taking into account the temperature dependence of the low-field mobility, saturation velocity, and inversion charge. The model correctly reproduces Sentaurus simulation data for the typical bias range used in integrated circuits. Lattice temperatures predicted by simulation are coherently reproduced by the model for varying silicon layer geometry.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlNx) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlNx) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.

Comparison and improvement of two core compact models for double-gate MOSFETs

In this paper, two present compact models for generic undoped double-gate (DG) MOSFETs are compared and discussed from aspects of formulations, advantages, prediction result, and computational efficiency. The models under comparison make fundamental contributions to generic DG MOSFET modeling. However, the applications of these models are hindered by their own drawbacks which are discussed in this work. The comparison results will provide a very useful reference and may benefit the future work for researchers to improve the development of double-gate MOSFET compact model. In addition, the calculation efficiency is extensively improved based on the Jacobian-Newton iterative method with a universal initial guess.

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C–V and I–V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.

Explicit quantum potential and charge model for double-gate MOSFETs

Abstract In this paper, we present a compact quantum model for both the electrostatic potential and electric charge in thin-film symmetric double-gate metal–oxide-semiconductor field-effect transistors with undoped body. As a novelty, both the resulting potential and charge have explicit expressions on bias and geometrical parameters. A comparison has been made between self-consistent numerical solutions of Schrodinger–Poisson equations and our model results with close agreement. Finally, the range of validity of the presented model is discussed.

Accurate prediction of the volume inversion impact on undoped Double Gate MOSFET capacitances

This paper demonstrates the capability of our previously published undoped Double-Gate (DG) MOSFET explicit and analytical compact model to also forecast the effect of the volume inversion (VI) on the intrinsic capacitances. For that purpose, we present simulation results for these capacitances. We show now that the model presents an accurate dependence on the silicon layer thickness, consistent with two-dimensional numerical simulations, for both thin and thick silicon films. As opposed to our previous work, here we test the capacitance model for three different film thicknesses and also show that the transition from VI regime to dual gate behaviour is well simulated. We demonstrate in this paper that even if the current drive and transconductance are enhanced in VI regime, our results show that intrinsic capacitances are higher as well, which may limit the high-speed (delay time) behaviour of DG MOSFETs under VI regime. The good agreement between the numerical simulations and our model shows the high potential of our complete DG MOSFET model. Copyright © 2010 John Wiley & Sons, Ltd.

A Review on Compact Modeling of Multiple-Gate MOSFETs

This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs. Long-channel core models based on the analytical potential solutions of Poisson and current continuity equations for symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs have been developed first. Highly accurate explicit solutions are subsequently developed to deal with the implicit algebraic equations of the models. By adding quantum mechanical effects and short-channel effects, as well as capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware. With regard to the various other types of MG MOSFETs developed, the core models for DG and SG MOSFETs have been generalized to the less symmetric structures, including quadruple-gate (QG), triple-gate (TG), ?-gate, and ?-gate MOSFETs. Other research activities on multiple-gate MOSFETs are briefly summarized at the end.

Implementation of the symmetric doped double‐gate MOSFET model in Verilog‐A for circuit simulation

AbstractRecently we developed a model for symmetric double‐gate MOSFETs (SDDGM) that, for the first time, considers the doping concentration in the Si film in the complete range from 1×1014 to 3×1018 cm−3. The model covers a wide range of technological parameters and includes short channel effects. It was validated for different devices using data from simulations, as well as measured in real devices. In this paper, we present the implementation in Verilog‐A code of this model, which allows its introduction in commercial simulators. The Verilog‐A implementation was optimized to achieve reduction in computational time, as well as good accuracy. Results are compared with data from 2D simulations, showing a very good agreement in all transistor operation regions. Copyright © 2009 John Wiley &amp; Sons, Ltd.