Power Dissipation Model Research Articles

Ultra Low Power Signal Oriented Approach for Wireless Health Monitoring

In recent years there is growing pressure on the medical sector to reduce costs while maintaining or even improving the quality of care. A potential solution to this problem is real time and/or remote patient monitoring by using mobile devices. To achieve this, medical sensors with wireless communication, computational and energy harvesting capabilities are networked on, or in, the human body forming what is commonly called a Wireless Body Area Network (WBAN). We present the implementation of a novel Wake Up Receiver (WUR) in the context of standardised wireless protocols, in a signal-oriented WBAN environment and present a novel protocol intended for wireless health monitoring (WhMAC). WhMAC is a TDMA-based protocol with very low power consumption. It utilises WBAN-specific features and a novel ultra low power wake up receiver technology, to achieve flexible and at the same time very low power wireless data transfer of physiological signals. As the main application is in the medical domain, or personal health monitoring, the protocol caters for different types of medical sensors. We define four sensor modes, in which the sensors can transmit data, depending on the sensor type and emergency level. A full power dissipation model is provided for the protocol, with individual hardware and application parameters. Finally, an example application shows the reduction in the power consumption for different data monitoring scenarios.

Energy efficient sequential sensing in multi-user cognitive ad hoc networks: A consideration of an ADC device

Cognitive networks (CNs) are capable of enabling dynamic spectrum allocation, and thus constitute a promising technology for future wireless communication. Whereas, the implementation of CN will lead to the requirement of an increased energy-arrival rate, which is a significant parameter in energy harvesting design of a cognitive user (CU) device. A well-designed spectrum-sensing scheme will lower the energy-arrival rate that is required and enable CNs to self-sustain, which will also help alleviate global warming. In this paper, spectrum sensing in a multi-user cognitive ad hoc network with a wide-band spectrum is considered. Based on the prospective spectrum sensing, we classify CN operation into two modes: Distributed and centralized. In a distributed network, each CU conducts spectrum sensing for its own data transmission, while in a centralized network, there is only one cognitive cluster header which performs spectrum sensing and broadcasts its sensing results to other CUs. Thus, a wide-band spectrum that is divided into multiple subchannels can be sensed simultaneously in a distributed manner or sequentially in a centralized manner. We consider the energy consumption for spectrum sensing only of an analog-to-digital convertor (ADC). By formulating energy consumption for spectrum sensing in terms of the subchannel sampling rate and whole-band sensing time, the sampling rate and whole-band sensing time that are optimal for minimizing the total energy consumption within sensing reliability constraints are obtained. A power dissipation model of an ADC, which plays an important role in formulating the energy efficiency problem, is presented. Using AD9051 as an ADC example, our numerical results show that the optimal sensing parameters will achieve a reduction in the energy-arrival rate of up to 97.7% and 50% in a distributed and a centralized network, respectively, when comparing the optimal and worst-case energy consumption for given system settings.

Power Dissipation Analysis of IEEE 802.15.4 Distributed Multi-Hop Wireless Sensor Networks

The involvement of IEEE 802.15.4 Wireless Sensor Networks (WSNs) in diverse applications has made the realistic analysis of sensor power dissipation in distributed network environments an essential research issue. In this paper, we propose and thoroughly analyze a power dissipation model for Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) based IEEE 802.15.4 distributed multi-hop WSNs. Our model takes the loss rate of frames, neighbor sensors density in communication range of a sensor, number of hops, distance of source to the sink, and density of the network into account. We evaluate the impact of these factors on overall power dissipation. We also perform comprehensive analysis of overheads caused by message routing through multi-hop distributed networks. We validate our proposed model through Monte Carlo simulations. Results show that our power dissipation model is more realistic compared to other proposed models in terms of accuracy and multiplicity of the environments.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

SIMULATION IN THERMAL DESIGN FOR ELECTRONIC CONTROL UNIT OF ELECTRONIC UNIT PUMP

The high working junction temperature of power component is the most common reason of its failure.So the thermal design is of vital importance in electronic control unit(ECU)design.By means of circuit simulation,the thermal design of ECU for electronic unit pump(EUP)fuel system is applied.The power dissipation model of each power component in the ECU is created and simulated. According to the analyses of simulation results,the factors which affect the power dissipation of components are analyzed.Then the ways for reducing the power dissipation of power components are carried out.The power dissipation of power components at different engine state is calculated and analyzed.The maximal power dissipation of each power component in all possible engine state is also carried out based on these simulations.A cooling system is designed based on these studies.The tests show that the maximum total power dissipation of ECU drops from 43.2 W to 33.84 W after these simulations and optimizations.These applications of simulations in thermal design of ECU can greatly increase the quality of the design,save the design cost and shorten design time

The Role of Optics and Electronics in High-Capacity Routers

This paper examines the role of optical and electronic technologies in future high-capacity routers. In particular, optical and electronic technologies for use in the key router functions of buffering and switching are compared. The comparison is based on aggressive but plausible estimates of buffer and switch performance projected out to around 2020. The analysis of buffer technologies uses a new model of power dissipation in optical-delay-line buffers using optical fiber and planar waveguides, including slow-light waveguides. Using this model together with models of storage capacity in ideal and nonideal slow-light delay lines, the power dissipation and scaling characteristics of optical and electronic buffers are compared. The author concludes that planar integrated optical buffers occupy larger chip area than electronic buffers, dissipate more power than electronic buffers, and are limited in capacity to, at most, a few IP packets. Optical fiber-based buffers have lower power dissipation but are bulky. The author also concludes that electronic buffering will remain the technology of choice in future high-capacity routers. The power dissipation of high-capacity optical and electronic cross connects for a number of cross connect architectures is compared. The author shows that optical and electronic cross connects dissipate similar power and require a similar chip area. Optical technologies show a potential for inclusion in high-capacity routers, especially as the basis for arrayed-waveguide-grating-based cross connects and as components in E/O/E interconnects. A major challenge in large cross connects, both optical and electronic, will be to efficiently manage the very large number of interconnects between chips and boards. The general conclusion is that electronic technologies are likely to remain as integral components in the signal transmission path of future high-capacity routers. There does not appear to be a compelling case for replacing electronic routers with optically transparent optical packet switches

Dynamic Task-Level Voltage Scheduling Optimizations

Energy versus delay trade-offs are explored for systems that must manage energy expenditure as well as computation deadlines. The focus is execution of a single process on a single processor. Two probabilistic process models are considered, along with a family of power dissipation models. The first process model assumes that process complexity is exactly c cycles with probability p(c). The second model considers the detailed branching and loop structure of the code. Probabilities are attached at branch points. The power models assume that energy dissipation per cycle is proportional to v/sup m/ and that execution time for a cycle is proportional to v/sup -n/, where v is supply voltage. The energy versus delay trade-off is implemented using dynamic voltage and clock adjustments. The problems solved include 1) minimize expected execution time given a hard energy budget and 2) minimize expected energy expenditure given a hard deadline. The problem of minimizing the expected value of Q(E,T), where Q is a penalty function and E and T are, respectively, total energy and total time, is also solved using the first process model. Analysis determines theoretical conditions where it may be profitable to switch voltage or modify an a priori voltage schedule.

Current-mode signaling in deep submicrometer global interconnects

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.

Temperature character of electromagnetic levitation melting

Utilizing the formula of electromagnetic force and input power, we have derived the expression of input power of a spherical sample for a general electromagnetic levitation inductor without including the current of the inducer. Combining the power dissipation model of the spherical sample in free-convection gas medium and the expression of input power without including the current of inducer, the relation between processing parameters of electromagnetic levitation and temperature of levitation sample is established. The electromagnetic melting of spherical (TbDy)Fe2 alloys under the protection of Ar is employed as an example to study the effect of processing parameters on the temperature of levitation sample obtained by numerical computation. According to computation results and the character of actual electromagnetic levitation, the methods to decrease the temperature of the levitation melted sample are obtained: i.e. reducing the radius of the levitation melted sample, employing low frequencies of the inducer, adjusting the position of the levitated sample to a position at which the lowest levitation melting temperature can be obtained, reducing the radius of the lower levitation coil, increasing the space interval between the upper stability controlling coil and the lower levitation coil, increasing the radius of the upper stability controlling coil, and increasing the turns of the upper stability controlling coil.

Powerdissipation in nanoscale conductors

A previous tight-binding model of power dissipation in ananoscale conductor under an applied bias is extended to takeaccount of the local atomic topology and the local electronicstructure. The method is used to calculate the power dissipatedat every atom in model nanoconductor geometries: a nanoscaleconstriction, a one-dimensional atomic chain between twoelectrodes with a resonant double barrier, and an irregularnanowire with sharp corners. The local power is compared with the local current density and the local density of states. Asimple relation is found between the local power and the currentdensity in quasiballistic geometries. A large enhancement in thepower at special atoms is found in cases of resonant andanti-resonant transmission. Such systems may be expected to beparticularly unstable against current-induced modifications.

Fully coupled electrothermal mixed-mode device simulation of SiGe HBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the /spl mu/A709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation.

Low-power system-level design of VLSI packet switching fabrics

System-level design of packet switching fabrics focuses on performance metrics and rarely considers the physical requirements that are usually addressed later at the circuit-level. However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologies. This paper proposes a framework for system-level design of packet switching fabrics that integrates performance specifications along with physical requirements and constraints. Moreover, realistic traffic models are used to derive the transition activity and the packet arrival and departure events needed for power estimation. Physical requirements are defined by an architectural model for power dissipation based on the stochastic traffic model, models for silicon area, chip count, and input-output pins, which provide a complete system-level specification of the fabric. Performance constraints are also derived from the stochastic traffic model. This framework formulates and solves the power optimization problem subject to those physical and performance constraints as an integer nonlinear optimization problem. The results obtained emphasize the importance of traffic-driven system-level optimization and show the efficiency of this framework as a system-level design space exploration tool.

Time-domain model for power dissipation of CMOSbuffers driving lossy lines

The dynamic power consumption of a CMOS buffer driving lossless and lossy transmission lines is investigated. A time-domain model for power dissipation in both the line driver and the interconnect losses is also presented. The model fully agrees with HSPICE simulations and is particularly suitable for implementation in CAD tools for fast estimation of VLSI dissipation circuits.

On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V.

Peculiarities of the vortex dynamics in YBa 2Cu 3O x single crystals as revealed by irreversible microwave absorption

We report the results of a wide experimental study of the irreversible modulated microwave absorption as a function of temperature, applied magnetic field and modulation amplitude in the YBa 2Cu 3O x single crystals. To analyze the experimental data the model of the microwave power dissipation by the flux lines has been developed taking into account thermal fluctuations, the distributions of currents and vortices over a sample. We have obtained the information about regimes of vortex motion in the different areas of the H– T phase diagram and estimated the values of flux flow viscosity and critical current density.

A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.

Vortex phase diagram in YBa2Cu3Ox and Bi2Sr2CaCu2Ox via the MMWA hysteresis

The hysteresis of modulated microwave absorption (MMWA) was studied as a function of temperature and DC magnetic field in single crystals of oxide superconductors YBa2Cu3Ox and Bi2Sr2CaCu2Ox using a standard X-band ESR-spectrometer. The analysis of experimental results is based on the model of the microwave power dissipation by the flux lines oscillating around their equilibrium positions which are governed by thermal fluctuations and the current distribution.