Mobility Of Thin-film Transistors Research Articles

High mobility and hysteresis free InGaSnO thin film transistors by co-sputtering via low temperature post annealing process

In this work, InGaSnO thin film transistors (TFTs) with high mobility (>50 cm2/Vs) were prepared by a simple co-sputtering process at a low temperature of 150 ℃. In the co-sputtering process of InSnO and Ga2O3, the composition of InGaSnO can be reasonably controlled by adjusting the sputtering power in the radio frequency plasma, which significantly affects the electrical performance and stability of InGaSnO TFTs. The highly overlapping 5 s electron cloud of In and Sn and the high binding energy of Sn-O lay the foundation for the high mobility of InGaSnO TFTs. The defects related to oxygen in the channel are suppressed by the reasonable control of the composition of Ga in the multicomponent oxides. Meanwhile, the interface defects between the gate dielectric and the active layer are reduced, and a dense metal-oxygen-metal network is formed which is conducive to electron transmission. We have achieved an InGaSnO TFTs with mobility of 58.7 cm2/Vs and threshold voltage of -1.33 V. The stability under positive and negative bias stress is also significantly improved. In general, a simple co-sputtering process is entirely feasible to realize high-mobility oxide TFTs. The control of the process temperature below 150 ℃ also extends its application in flexible electronic devices.

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway.

Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures offer promising alternative materials for next-generation high-density memory devices. The complex vertical stacking process of memory devices significantly increases the probability of encountering internal contact issues. Conventional surface treatment methods developed for planar devices necessitate efficient approaches to eliminate contact issues at deep internal interfaces in the nanoscale complex structures of AOS devices. In this work, we report the pioneering use of palladium thin film as a high-efficiency active hydrogen transfer pathway from the outside to the internal contact interface via low-temperature postannealing in the H2 atmosphere, and the formation of highly conductive metallic interlayer effectively solves the contact issues at the deeply buried interfaces in devices. The application of this method reduced the contact resistance of Pd electrodes/amorphous indium-gallium-zinc oxide (a-IGZO) thin-film by 2 orders of magnitude, and thereby the mobility of thin-film transistor was increased from 3.2 cm2 V-1 s-1 to nearly 20 cm2 V-1 s-1, preserving an excellent bias stress stability. This technology has wide applicability for the solution of contact resistance issues in oxide semiconductor devices with complex architectures.

Electrical performance of La-doped In2O3 thin-film transistors prepared using a solution method for low-voltage driving.

In this paper, La-doped In2O3 thin-film transistors (TFTs) were prepared by using a solution method, and the effects of La doping on the structure, surface morphology, optics, and performance of In2O3 thin films and TFTs were systematically investigated. The oxygen defects concentration decreased from 27.54% to 17.93% when La doping was increased to 10 mol%, and La served as a carrier suppressor, effectively passivating defects such as oxygen defects. In fact, the trap density at the dielectric/channel interface and within the active layer can be effectively reduced using this approach. With the increase of La concentration, the mobility of LaInO TFTs decreases gradually; the threshold voltage is shifted in the positive direction, and the TFT devices are operated in the enhanced mode. The TFT device achieved a subthreshold swing (SS) as low as 0.84 V dec-1, a mobility (μ) of 14.22 cm2 V-1 s-1, a threshold voltage (VTH) of 2.16 V, and a current switching ratio of Ion/Ioff of 105 at a low operating voltage of 1 V. Therefore, regulating the doping concentration of La can greatly enhance the performance of TFT devices, which promotes the application of such devices in high-performance, large-scale, and low-power electronic systems.

Inkjet printing high mobility indium-zinc-tin oxide thin film transistor

Metal oxide thin film transistor has been widely used in flat panel display industry because of its low leakage current, high mobility and large area uniformity. Besides with the development of printed display technology, inkjet printing process can fabricate the customizable patterns on diverse substrates without the need for vacuum or lithography, can significantly reduce cost and has received more and more attention. In this paper, we fabricate a bottom gate bottom contact structure thin film transistor (TFT) with indium-zinc-tin-oxide (IZTO) semiconductor using inkjet printing process. The surface morphology of the printed IZTO film is modified by adjusting the solvent composition and solute concentration of the printing precursor ink. The experimental result show that the use of binary solvents can effectively overcome the coffee ring shape caused by the accumulation of solute edge during the volatilization process of a single solvent, and finally show a uniform and flat contour surface. Further increase in solute concentration is in favor of formation of convex surface topology. The reason for the formation of the flat surface of the oxide film is the balance between the inward Marangoni reflux of the solute and the outward capillary flow during volatilization. In addition, using binary solvents printed IZTO thin film transistor exhibit excellent electrical properties. The ratio of width/length=50/30 exhibit a high on-off ratio of 1.21×10<sup>9</sup>,a high saturation field-effect mobility of 16.6 cm<sup>2</sup>·V<sup>-1</sup>·s<sup>-1</sup>,a low threshold voltage of 0.84 V and subthreshold swing of 0.24 V/dec. The uniform and flat active layer thin film pattern can form good contact with the source leakage electrode, and the contact resistance of TFT devices with different width-to-length ratios is less than 1000 Ω, which can achieve the basic conditions of high mobility thin film transistors prepared by inkjet printing. Therefore, using mixture solvents provides a universal and facile way to print oxide films with desired surface topology and provide a visible path for inkjet printing of high-mobility thin film transistors.

Effect of Metal Capping Layer in Achieving Record High p-Type SnO Thin Film Transistor Mobility

Effect of Metal Capping Layer in Achieving Record High p-Type SnO Thin Film Transistor Mobility

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

Single‐layer thin‐film transistor analysis and design

AbstractA set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short‐base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.

High‐performance, coplanar amorphous InGaZnO thin‐film transistors by spray pyrolysis on polyimide substrate for low‐cost manufacturing of foldable active‐matrix organic light emitting diode display

AbstractWe report a method for low‐cost deposition of bubble‐free, high‐quality amorphous InGaZnO (a‐IGZO) on polyimide (PI) substrate for foldable active‐matrix organic light emitting diode (AMOLED) display by spray pyrolysis. The coplanar thin‐film transistor (TFT) with spray‐pyrolyzed (SP) a‐IGZO on PI substrate exhibits threshold voltage (VTH) of −0.8 V, saturation mobility of 40.95 cm2 V−1 s−1, and subthreshold swing of 0.18 V per decade with on/off drain current ratio of ~108. The high mobility TFT could be achieved using high substrate temperature (350°C) and low contact resistance by NF3 plasma on the SP a‐IGZO. The TFT shows a ΔVTH of −0.4 V when it is bent on a cylinder of 1‐mm radius. The TFT shows the ΔVTH of +0.05 V for positive bias temperature stress at +20 V at 60°C for 1 h. The ring oscillator made of a‐IGZO TFTs exhibits an oscillation frequency of 2.38 MHz at VDD of 10 V with a propagation delay of 9.13 ns per stage. Therefore, the a‐IGZO TFT by spray pyrolysis could be used for low‐cost, high‐performance, and flexible display TFT backplane.

Enhancement of electrical properties of a-IGZO thin film transistor by low temperature (150 °C) microwave annealing for flexible electronics

A relatively low-temperature process is required to fabricate amorphous oxide thin film transistor (TFT) display backplanes for flexible electronics. However, in order to ensure the outstanding electrical property of TFT, a typical post-annealing process should be performed at 300 °C or above. This is not compatible with flexible substrates in the process. In our work, we applied microwave annealing (MWA) at a low-temperature (150 °C) to the oxide TFT and verified its feasibility through the evaluation of various electrical properties. Even an a-IGZO TFT by MWA at such a low-temperature shows high mobility (29.0 cm2/V s) by DC ID-VG measurement, which is 4 ∼ 5 times higher than other counterparts, indicating that the MWA process is very effective to minimize the defects in an oxide semiconductor channel. To further investigate the intrinsic mobility of TFT with negligible charge trapping, we carried out fast and pulse ID-VG measurement methods. The intrinsic mobility extracted from this measurement is found to be 35.3 cm2/V s, 21.7% higher than that of DC ID-VG. We are expecting that the low-temperature MWA process would be widely used for the process of oxide TFT in a flexible platform.

Editors’ Choice—Thin Film Transistor Response in the THz Range

Novel metal oxide materials such as InGaZnO (IGZO), ZnO, SnO, and In2O3 and improved fabrication processes dramatically enhanced the achieved and projected thin film transistor (TFT) performance. The record values of the effective field-effect mobility of Metal Oxide TFT (MOTFT) materials have approached 150 cm2/Vs. We report on an improved compact TFT model based on three models: the RPI TFT model, the unified charge control model (UCCM), and the multi-segment TFT compact model. This improved model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias, and parasitic impedances. The analysis of the TFT response using this model and the analytical calculations showed that TFTs could have a significant response to impinging THz and sub-THz radiation. Using a complementary inverter and the phase-matched THz signal feeding significantly improves the detection sensitivity.

Low-temperature solution-processed nanoparticle-doped nickel oxide thin-film transistor

Developing p-type oxide thin-film transistors (TFTs) is an essential path for further application in complementary metal oxide semiconductor (CMOS) components. However, the inferior electrical performance of p-type MO TFTs compared to n-type TFTs remains an ongoing challenge. Herein, for the first time, a low temperature, facile material engineering approach by incorporating n-type nanoparticles (NPs) was proposed for preparing p-type transparent NiOx TFTs. The characteristics of thin films blending NPs and the electrical performances of TFTs were investigated. The field effect mobility of TFTs with doping was nearly 20 times higher than pristine TFTs without doping, which was mainly beneficial from the suitable band alignment between NPs and p-type oxide, the increasing Ni3+ oxidation state in NiOx, as well as the improved dielectric/semiconductor interface quality. Electrons from drain electrode injected into metal oxide turn accepted in NPs rather than being trapped in the dielectric/semiconductor interface due to a strong surface electron depletion effect of NPs. NPs with small particle size and appropriate concentration would promote continuous hole transport by electrons transferring and reducing the interface trap state. The facile material engineering strategy is a promising technique for preparing p-type transparent MO-TFTs at low temperature, which showed great potential to be applicable in CMOS circuits on flexible substrates.

Outstanding High Field‐Effect Mobility of 299 cm2 V−1 s−1 by Nitrogen‐Doped SnO2 Nanosheet Thin‐Film Transistor

AbstractRecord high field‐effect mobility (µFE) thin film transistors (TFTs) based on 5 and 7 nm thickness SnON channel layer is reported. The SnON TFT device with 7.6% nitrogen content achieves a record high µFE of 299 cm2 V−1 s−1 at 7 nm thickness and 277 cm2 V−1 s−1 at 5 nm thickness, compared to SnO2 with µFE of 211 cm2 V−1 s−1. At the same 5 nm quasi‐2D channel thickness, this µFE of nanocrystalline SnON transistor is comparable to single crystalline Si and InGaAs metal oxide semiconductor field‐effect transistor (MOSFET) and also higher than the phonon‐scattering‐limited 2D MoS2 FET. From the principle of quantum‐mechanical calculation, the high µFE of nanosheet SnON TFT is due to lower effective mass of electrons, 0.29 m0 in the conduction band in contrast to 0.41 m0 of SnO2. SnON can reduce the defect trap densities by introducing non‐oxide anions where the valence band can be controlled to remove or passivate the oxygen vacancy levels by substitutional alloying with nitrogen anions to circumvent instability, increase on‐current (ION) and improve the µFE. It is highly expected that the high performance quasi‐2D nanosheet SnON TFTs will be utilized in embedded DRAM and monolithic 3D integrated circuits (ICs).

Field-Effect Mobility Extraction of Solution-Processed InGaZnO Thin-Film Transistors Considering Dielectric Dispersion Behavior of AlOx Gate Insulator

We investigated the effect of the dielectric dispersion behavior of solution-processed aluminum oxide (AlOx) on the field-effect mobility estimation of the solution-processed indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). In the metal–insulator–metal (MIM) structure, solution-processed AlOx dielectric film annealed at 350 °C showed dielectric dispersion behavior, which was attributed to the electric double layer (EDL) due to the mobile ions, such as a hydrogen ion (H+) or a hydroxyl group (OH–). The annealing process at a higher temperature of 500 °C reduced the number of mobile ions in the AlOx film and removed the dielectric dispersion behavior in the MIM structure. However, solution-processed IGZO TFTs using the AlOx annealed at 500 °C as gate insulator showed dielectric dispersion-related behavior. We found that the chemical reaction to form a solution-processed IGZO layer supplied the mobile ions to the AlOx film, resulting in the EDL and dielectric dispersion phenomenon. Therefore, the dielectric dispersion should be investigated in the metal–insulator–semiconductor–metal structure, although the dispersive behavior does not occur in the MIM structure. Furthermore, the field-effect mobility (μFE) of solution-processed IGZO TFTs was 35.6 and 17.5 cm2/V·s with and without consideration of the dielectric dispersion behavior. The μFE was overestimated by 203% without regard to the dielectric dispersion. Consequently, the dielectric dispersion should be considered to estimate the accurate μFE of solution-processed IGZO TFTs with solution-processed AlOx as the gate insulator layer.

High-pressure H2O post-annealing for improving reliability of LTPS and a-IGZO thin-film transistors within a coplanar structure

Improving reliability of low-temperature polycrystalline silicon (LTPS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs), components of low-temperature polycrystalline silicon and oxide (LTPO), is crucial for fabricating high-performance and high-stability LTPS and oxide semiconductor-based electronics and display products. However, improving the reliability of these TFTs simultaneously in a uniform and effective manner within a coplanar structure is challenging. In this work, high-pressure H2O post-annealing (H2O HPPA) as a post-treatment for LTPS and a-IGZO TFTs within a coplanar structure are proposed to improve the uniformity and stability of the electrical characteristics simultaneously. It was demonstrated that oxygen and hydrogen in the HPPA-passivated defect state at the channel/gate dielectric layer interfaces and bulk gate dielectric layers of LTPS and a-IGZO TFTs considerably improve the uniformity and stability of the electrical performance and morphologies of the interfaces. Thus, the distribution of electrical characteristics (mobility, threshold voltage, and subthreshold swing) in LTPS and a-IGZO TFTs was reduced by more than 2-fold, and the trap charge densities at their interfaces and bulk gate dielectric layers were reduced by approximately 1.6-fold. Furthermore, the threshold voltage shift was decreased in both LTPS and a-IGZO-TFTs fabricated with H2O HPPA under negative and positive bias temperature stresses, respectively. The proposed H2O HPPA method can effectively facilitate the industry-level application of LTPS and oxide semiconductor-based electronics and display electronics.

Synergistically Enhanced Performance and Reliability of Abrupt Metal‐Oxide Heterojunction Transistor

AbstractThe large‐area low‐temperature processing capability and versatile characteristics of amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) are highly expected to promote the developments of next‐generation displays, 3D integrated circuit (3DIC), flexible chips, and electronics. However, the abundant native defects in AOSs engrain an inherent trade‐off between high mobility and trustworthy stability in AOS TFTs, fundamentally limiting the performance metrics and integration scale of oxide‐based electronics. To surmount this obstacle, the bilayer AOS channel is highly expected to combine the merits of diversified AOSs, while the efficiency of such an AOS “heterojunction” is debatable. This work systematically compares the TFTs based on amorphous InGaZnO (a‐IGZO), amorphous InZnO (a‐IZO), and a‐IZO/a‐IGZO bilayer. The active cation interaction between metal‐oxide semiconductors gives rise to a mixed AOS layer rather than a heterojunction channel, corresponding to moderate performance metrics. Such a spontaneous cation interdiffusion is effectively prevented using a dense metal‐oxide dielectric interlayer, aluminum oxide (AlOx). The sharpened interface effectively forms an abrupt metal‐oxide heterojunction, while the electron can still tunnel through the ultrathin AlOx to create a quantum well of 2D electron gas (2DEG). The overall performance and reliability of multilayer AOS TFT are synergistically enhanced using the proposed abrupt metal‐oxide heterojunction architecture.

(Invited) Approach to Oxide Tfts with High Mobility & Stability

Thin film transistors (TFTs) with the channel of amorphous oxide semiconductors (AOSs) represented by amorphous Indium-Gallium-Zinc Oxide (a-IGZO) are now applied to drive pixels of the state-of the art display based on high mobility, good homogeneity, easy fabrication and optical transparency [1]. Recently, larger mobility TFTs are highly demanded for emerging applications such as ultra-high vision and memories. However, there is a critical obstacle to be overcome, i.e., an empirical trade-off rule in oxide TFTs between mobility and stability. Higher mobility TFTs possess less stability to various types of stress (negative bias-thermal stress instability, NBTS, positive bias-thermal stress instability, PBTS, and negative bias-illumination stress instability, NBIS). The Elucidation of origin for this trade-off rule and new approach are required to realize high mobility and high stability TFTs. We clarify that the origin of this trade-off through comparison in TFTs between IGZO with low mobility and high stability and ITZO with high mobility and low stability. A critical phenomenon was noted during the conventional TFT fabrication; CO-related impurity donates electrons to Indium-Tin-Zinc Oxide (ITZO) with high mobility under the negative bias stress condition but such CO-related impurity effect is negligible in IGZO with lower mobility than ITZO [2]. This finding may be understood by considering that large difference in ECBM determines the transfer of electron generated by adsorbed CO-related species on the back surface of ITZO [3]. Based on this model and this finding, we successfully fabricated the most stable ITZO TFT with a high mobility of 70 cm2/Vs by eliminating CO-related impurity and further passivation; NBTS (-20V, 60 oC, 3600 s, ΔVth: -0.02 V), PBTS (+20 V, 60 oC, 3600 s, ΔVth: 0.12 V) and NBIS (-20V, 15000 lx, 3600s, ΔVth: -1.33 V).[1] Hosono, H., & Kumomi,K., (ed), Amorphous Oxide Semiconductors: IGZO and Related Materials for Display and Memory (Wiley, 2022); Hosono, H. (2018). How we made the IGZO transistor. Nature Electronics, 1(7), 428-428.[2]Shiah, Y. S., Sim, K., Ueda, S., Kim, J., & Hosono, H. (2021). Unintended Carbon-Related Impurity and Negative Bias Instability in High-Mobility Oxide TFTs. IEEE Electron Device Letters, 42(9), 1319-1322.[3] Shiah, Y. S., Sim, K., Shi, Y., Abe, K., Ueda, S., Sasase, M., Kim,J., & Hosono, H. (2021). Mobility–stability trade-off in oxide thin-film transistors. Nature Electronics, 4(11), 800-807.

(Invited) Hydrogenated Polycrystalline In2O3 (In2O3:H) Thin-Film Transistor with High Mobility Exceeding 100 cm2V−1s−1 Via Solid-Phase Crystallization

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μ FE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µ FE = 139.2 cm2V−1s−1. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future electronic applications.

Optimisation of geometric aspect ratio of thin film transistors for low-cost flexible CMOS inverters and its practical implementation

A low-cost, flexible processor is essential to realise affordable flexible electronic systems and transform everyday objects into smart-objects. Thin film transistors (TFTs) based on metal-oxides (or organics) are ideal candidates as they can be manufactured at low processing temperatures and low-cost per unit area, unlike traditional silicon devices. The development of complementary metal–oxide–semiconductor (CMOS) technology based on these materials remains challenging due to differences in performance between n- and p-type TFTs. Existing geometric rules typically compensate the lower mobility of the metal-oxide p-type TFT by scaling up the width-to-length (W/L) ratio but fail to take into account the significant off-state leakage current. Here we propose the concept of an optimal geometric aspect ratio which maximises the inverter efficiency represented by the average switching current divided by the static currents. This universal method is especially useful for the design of low-power CMOS inverters based on metal-oxides, where the large off-current of the p-type TFT dominates the static power consumption of the inverter. We model the inverter efficiency and noise margins of metal-oxide CMOS inverters with different geometric aspect ratios and compare the performance to different inverter configurations. The modelling results are verified experimentally by fabricating CMOS inverter configurations consisting of n-type indium-silicon-oxide (ISO) TFTs and p-type tin monoxide (SnO) TFTs. Notably, our results show that reducing W/L of metal-oxide p-type TFTs increases the inverter efficiency while reducing the area compared to simply scaling up W/L inversely with mobility. We anticipate this work provides a straightforward method to geometrically optimise flexible CMOS inverters, which will remain relevant even as the performance of TFTs continues to evolve.

Study of high-pressure hydrogen annealing effects on InGaZnO thin-film transistors

High-pressure hydrogen annealing (HPHA) treatment is an effective hydrogen doping method to improve electrical characteristics and stability of InGaZnO (IGZO) thin film transistors (TFTs). The HPHA effects on IGZO TFTs under various pressure conditions were investigated using analytical techniques. Drive current, field effect mobility, subthreshold swing, and bias stress stability of IGZO TFTs were significantly improved as the HPHA pressure was increased up to 20 atm. To analyze the performance enhancement, secondary ion mass spectroscopy, capacitance–voltage analysis, and x-ray photoelectron spectroscopy analysis techniques were performed. As a result, it was confirmed that doped hydrogen is combined with interface trap sites and oxygen vacancy related bulk defect sites, leading to improved subthreshold swing and bias stress stability. Furthermore, bulk trap passivation also contributes to high carrier density, thereby increasing driving current and field effect mobility. With increasing HPHA pressure condition, these effects of trap passivation and increase in the carrier density are more effective due to the heavily injected hydrogen.

Design Concept of CT Plate Detector and CT Machine

Because the mobility ratio of thin film transistors is too low, it is recognized that flat detector can not be used in CT machine.The current research direction is to find the detector material with higher mobility ratio, but with little success. This study puts forward a new scheme to solve the core problem that limits the application of CT, which is the mobility of thin film transistors:by moving various TFT functions in the thin film transistor to the peripheral circuit, the restriction of the mobility of thin film transistor on the CT machine is completely overcome, and the reading speed of the flat panel detector becomes very fast, which can perfectly meet the requirements of the scanning speed of the CT machine.This will provide new research ideas for the application of flat panel detector in CT machine.