Mobility In MOSFETs Research Articles

Increasing Mobility in 4H-SiC MOSFETs with Deposited Oxide by <i>In-Situ</i> Nitridation of SiC Surface

We present the improvement of SiO2/4H-SiC interface quality and high field-effect (FE) mobility (µFE) in 4H-SiC MOSFETs. This is achieved by introducing a nitrous oxide (N2O) plasma in-situ pre-treatment before gate stack formation using plasma enhanced chemical vapour deposition (PECVD) oxide followed by a post deposition anneal (PDA) in diluted N2O for times ranging from 30 to 120 minutes thereby creating an ultra-thin thermally grown SiO2 layer at the SiO2/4H-SiC interface. MOS capacitors with SiO2 deposited on in-situ pre-treated SiC surfaces had a lower density of interface traps (DIT) for all PDA durations, compared with devices having untreated PECVD oxides or control devices with 30 nm thermally grown oxide. After PDA for 90 minutes, a minimum DIT value of 1.2×1011 cm-2·eV-1 was measured. A peak µFE value reaching 94 cm2/(V·s) was measured in n-channel planar MOSFETs fabricated with PECVD oxide on in-situ pre-treated devices, which significantly exceeds a maximum µFE of 6 cm2/(V·s) in control devices.

Enhanced field-effect mobility (>250 cm2/V·s) in GaN MOSFETs with deposited gate oxides via mist CVD

We report an enhanced field-effect mobility (>250 cm2·V−1·s−1) in GaN MOSFETs. High mobility was achieved by reducing the oxidation of the GaN surface, which was a major factor affecting channel mobility in GaN MOSFETs. Among various gate oxide deposition methods, mist CVD using O3 suppressed GaN surface oxidation. The best field-effect mobility was observed using mist CVD-deposited gate oxides, achieving a peak mobility of 266 cm2·V−1·s−1 with a high threshold voltage of 4.8 V.

Mg activation anneal of the p-GaN body in trench gate MOSFETs and its effect on channel mobility and threshold voltage stability

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs.

The effect of biaxial strain on the phonon-limited mobility in 4H-SiC MOSFETs

We investigate the effect of biaxial tensile stress at the interface of 4H-SiC metal-oxide-semiconductor field effect-transistors on the phonon-limited mobility using theoretical calculations. The band structure under strain is obtained by the first-principles calculations, and the electronic states and potential of the inversion layer at the interface are determined by the Schrödinger–Poisson method. The mobility is calculated using the Fermi's golden rules. We find that the biaxial strain reduces the energy difference between the first and second conduction band minima. This leads to an increase in polar-optical phonon scattering, which becomes the dominant factor in the mobility degradation under the tensile strain.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.

Increased Mobility in 4H-SiC MOSFETs by Means of Hydrogen Annealing

Enhancement-mode 4H-SiC MOSFETs utilising an aluminium oxide (Al2O3) dielectric without the requirement for an underlying silicon oxide (SiO2) layer have been shown to have a field effect mobility of 150 cm2V−1s−1 and a subthreshold swing of 160 mV/dec. The fabricated devices utilised a forming gas (3% H2 in N2) anneal immediately prior to the deposition of the Al2O3 by Atomic Layer Deposition (ALD). A comparison MOSFET using an identical Al2O3 deposition process with a 0.7 nm SiO2 layer had a field effect mobility of approximately 20 cm2V−1s−1. The hydrogen annealed device had a lower density of interface traps (Dit), a lower subthreshold swing, and a significantly reduced hysteresis in the transconductance data than the thin SiO2 sample. This finding solves the issue of inconsistency of device performance using thin film gate dielectric as an interfacial layer by offering a simple and controllable process.

Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

The inversion channel electron mobility in 4H-SiC MOSFETs with NO annealed gate oxides is still well below its theoretical limit. The physical reason behind the reduced mobility is not yet fully established but has for example been attributed to a high density of very fast interface traps close to the conduction band edge. These traps are not detected by high-low CV analysis at room temperature but are observed by conductance spectroscopy at low temperatures. In this study we demonstrate how conventional high-low CV analysis of MOS capacitors at cryogenic temperatures can be applied to detect and quantify these very fast traps.

Dipole scattering at the interface: The origin of low mobility observed in SiC MOSFETs

In this work, the origin of the low free electron mobility in SiC MOSFETs is investigated using the scattering theory of two-dimensional electron gases. We first establish that neither phonon scattering nor Coulomb scattering can be the cause of the low observed mobility in SiC MOSFETs; we establish this fact by comparing the theoretically calculated mobility considering these effects with experimental observations. By considering the threshold voltages and the effective field dependence of the mobility in SiC MOSFETs, it is concluded that the scattering centers of the dominant mechanism are electrically neutral and exhibit a short-range scattering potential. By considering a charge distribution around a neutral defect at the interface, it is established that an electric dipole induced by the defect can act as a short-range scattering potential. We then calculate the mobility in SiC MOSFETs assuming that there exists a high density of dipoles at the interface. The calculated dipole-scattering-limited mobility shows a similar dependence on the effective field dependence to that observed in experimental results. Thus, we conclude that scattering induced by a high density of electric dipoles at the interface is the dominant cause of the low mobility in SiC MOSFETs.

Case Study of Semiconducting Material

This electronic document is a “live” template and already There is no doubt that semiconductors changed the world beyond anything that could have been imagined before them. Although people have probably always needed to communicate and process data, it is thanks to the semiconductors that these two important tasks have become easy and take up infinitely less time than, e.g., at the time of vacuum tubes. Semiconductor materials are the building blocks of the entire electronics and computer industry. Small, lightweight, high speed, and low power consumption devices would not be possible without integrated circuits (chips), which consist of semiconductor materials. This paper provides a general discussion of semiconductor materials, their history, classification and the temperature effects in semiconductors. In this section we provide details about the impact of temperature on the MOSFET energy band gap, carrier density, mobility, carrier diffusion, velocity saturation, current density, threshold voltage, leakage current and interconnect resistance. We also provide the applications of semiconductor materials in different sectors of modern electronics and communications.

Evaluation methods of channel mobility in MOSFETs

Evaluation methods of channel mobility in MOSFETs

Experimental Determination of Interface Trap Density and Fixed Positive Oxide Charge in Commercial 4H-SiC Power MOSFETs

We measure interface trap density near the conduction band edge and fixed oxide charge in commercial, packaged, 4H-SiC 1.2 kV planar Power MOSFETs. These traps determine the device threshold voltage, performance, and reliability. The subthreshold slope is used to extract interface trap density at the SiO2-SiC interface near the conduction band edge from three vendors, which varies from $5.8\times 10 ^{12}$ to $9.3\times 10 ^{12}$ cm $^{-2}\cdot $ eV−1. Good agreement is obtained with threshold voltage measurements from 25°C to 150°C as devices with the highest interface trap densities exhibit the largest threshold voltage reduction over temperature. Fixed positive oxide charge, $N_{ot}$ , balanced with interface traps and substrate doping, varies from $3.3\times 10 ^{12}$ cm−2 to $3.7\times 10 ^{12}$ cm−2. At high temperatures, electrons captured in interface traps emit to the conduction band and lower the threshold voltage together with fixed oxide charges, which are as high as interface trap densities. Thus, device design should be considered for a suitable threshold voltage to ensure the device does not operate in a Normally-ON condition and to protect against gate voltage surges. Therefore, more focus on characterization and reduction of the interface trap density and fixed oxide charge is needed to enable further improvement in effective electron mobility of SiC MOSFETs.

Fast Near-Interface Traps in 4H-SiC MOS Capacitors Measured by an Integrated-Charge Method

Oxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs.

(Invited) Border-Trap Characterization for Ge Gate Stacks with Thin GeOX layer Using Deep-Level Transient Spectroscopy

1) Introduction Ge is one of the candidate materials for the future high performance MOSFET. In order to embody the high performance Ge-MOSFET, stacked gate dielectrics with thin Ge oxide interlayer, such as SiO2/GeO2 and Al2O3/GeOx, have been studied actively [1, 2]. On the other hand, in the case of Ge-MOS gate stacks, not only interface traps (ITs) but border traps (BTs) located in gate dielectric are also problematic because they degrade MOS characteristics and mobility of the MOSFET. For deep understanding and performance improvement of Ge MOS gate stacks, both density and position of BT in stacked gate dielectrics should be clarified. However, in-depth study of BT in Ge gate stacks is limited.Recently, we succeeded in separating the BT and IT signals using deep-level transient spectroscopy (DLTS) in SiO2/GeO2/Ge gate stacks grown by thermal and plasma oxidation [3,4].In this study, the densities of IT (D it) and BT (N bt) in Al2O3/GeOx/p-Ge gate stacks grown by post plasma oxidation (PPO) were evaluated. In addition, to study the relationship between BTs and mobility of devices, Ge p-MOSFETs with Al2O3/GeOx/Ge gate stacks were also fabricated and characterized. The effect of BTs on the mobility of MOSFETs is also discussed. 2) Experimental P-type (100) Ge substrate with a doping concentration of 2.3×1016 cm-3 was used. After chemical cleaning by HF solution, the first layer of Al2O3 was deposited at 300°C by ALD with precursors of water and trimethylaluminum for 3, 9, 14 and 20 cycles, corresponding to four samples, followed by PPO using electron cyclotron resonance (ECR) at room temperature. The GeOx thicknesses in Al2O3 gate stacks with 3, 9, 14 and 20 ALD cycles were 0.87, 0.42, 0.06, and 0.16 nm, respectively. The second layer of Al2O3 was deposited at 300°C by ALD for 25 cycles to avoid current leakage during electrical measurements. A 400°C post-deposition annealing for 30 min was performed. Then, the TiN layer was deposited by sputtering, followed by 350°C post-metallization annealing for 20 min. After that, the Al layer was also deposited and gate electrode was patterned. To improve the electrical contact between TiN and Al layers, a contact annealing was performed at 300°C for 10 min. Finally, an InGa back contact was formed.Ge p-MOSFETs were fabricated on n-type (100) Ge substrate with a doping concentration of 9.3 × 1015 cm-3. We used a gate-first process. An Al2O3/GeOx/Ge gate stack was fabricated by the same method as MOS capacitors as mentioned above. The source/drain (S/D) region was fabricated using B ion implantation, followed by the activation annealing (for S/D) at 300°C for 10 min. The active hole density of 4.3×1019 cm-3 was confirmed by Hall Effect measurement. 3) Summary of the r esults ITs and BTs in Al2O3/GeOx/p-Ge gate stacks were characterized using DLTS. Through evaluating the gate stacks with different GeOx thickness, the respective BTs in Al2O3, Al2O3/GeOx interface region, and GeOx were successfully detected. The D it near to mid-gap is lower in the MOS capacitors with a thicker GeOx, while the D it near to valence band is lower in the MOS capacitor with a thinner GeOx, which is probably due to the defect termination by Al oxide. The N bt in Al2O3 was 6~9×1017 cm-3, which is lower than those in GeOx (~2×1018 cm-3), and the highest N bt of ~1×1019 cm-3 was found in Al2O3/GeOx interface region.Ge p-MOSFETs with Al2O3/GeOx/p-Ge gate stacks were analyzed. It was confirmed that the ITs and the BTs near to valence band edge of Ge affect the effective mobility of Ge p-MOSFETs in high field region. Therefore, reduction of ITs and BTs near to valence band is the key to reach high-performance p-MOSFETs. In this sense, Al2O3 is a suitable dielectric material for Ge p-MOSFETs. Acknowledgement This work was partially supported by (JSPS) KAKENHI (grant numbers 17H03237 and 18KK0134) and Advanced Graduate Program in Global Strategy for Green Asia, Kyushu University.

Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress

We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stress in [110] direction applied to a (001) film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the dependence of the non-parabolicity parameter on film thickness and strain. The influence of the subband structure modification on the mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. It is shown that an increase of subband non-parabolicity in thin films with strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values.

Spatial scale dependent impact of non-uniform interface defect distribution on field effect mobility in SiC MOSFETs

Understanding the properties of SiO2/SiC interfaces is one of the key issues related to the development of SiC power devices. However, existing evaluation methods such as capacitance-voltage measurements do not directly provide microscopic assessments. Recently, the nanoscale imaging of interface defect density distributions has become possible using local deep level transient spectroscopy. This technique has shown that the defect density at a SiO2/SiC interface can have a non-uniform, clustered distribution. Prior numerical simulations by our group have also demonstrated that this inhomogeneous clustering of interface defects may reduce field effect mobility in SiC metal oxide field effect transistors. The present work examines the relationship between the spatial scale of the non-uniformity and reductions in field effect mobility and shows that an interface defect distribution containing smaller features will have a greater effect on field effect mobility.

Dominant scattering mechanism in SiC MOSFET: comparative study of the universal mobility and the theoretically calculated channel mobility

The universal mobility in SiC MOSFETs is investigated and compared with the theoretically calculated channel mobility. From an analysis of channel mobility of SiC MOSFETs with sufficiently reduced Coulomb scattering centers, it is quantitatively shown that η, which determines effective electric fields Eeff (=q(Ndpl + η Ns)/εs), should be set to 0.26 to express the mobility universally. Acoustic-phonon scattering-limited mobility, intervalley-scattering-limited mobility, and roughness-scattering-limited mobility are calculated and compared with the universal mobility. Consequently, it is shown that acoustic phonon scattering is dominant in a wide Eeff range, whereas roughness scattering has a slight effect in a high Eeff range, and the influence of intervalley-scattering is limited throughout the Eeff range. In particular, it is shown that acoustic phonon scattering between the 1st conduction band minima (CBM) and 2nd CBM, which exists 120 meV above the 1st CBM, greatly limits mobility of SiC MOSFETs.

Modeling of carrier scattering in MOS inversion layers with large density of interface states and simulation of electron Hall mobility in 4H-SiC MOSFETs

We formulate scattering mechanisms in quasi-two-dimensional systems with a large density of interface states such as 4H-SiC MOS interfaces, and calculate the electron Hall mobility in 4H-SiC MOS inversion layers by Monte Carlo simulation. In addition to phonon, ionized impurity, and surface roughness scattering, we take account of Coulomb scattering by the electrons trapped at the interface states and the interface fixed charges and scattering by electrically neutral defects. Considering that the number of trapped electrons can be comparable to or larger than that of mobile electrons, the trapped electrons are assumed to contribute to screening as well as scattering. Using the developed model, we analyze the dependence of Hall mobility in 4H-SiC MOS inversion layers on the body acceptor density, temperature, and interface state density. Our calculation reasonably reproduces the experimental behaviors of Hall mobility. We also discuss the physical mechanisms underlying the obtained results.

Influences of pre-oxidation nitrogen implantation and post-oxidation annealing on channel mobility of 4H-SiC MOSFETs

Detailed investigations on the pre-oxidation nitrogen implantation and post-oxidation annealing processes for the improvement of channel mobility and specific on-resistance in 4H-SiC MOSFETs are reported. The results indicate that higher temperature and time for NO nitridation annealing process lead to higher field-effect channel mobility and lower specific on-resistance attributed to the good interface properties of SiC and SiO2 of MOSFETs. Furthermore, more nitrogen implantation energy and dose improved the channel mobility and specific on-resistance due to higher Id and less fixed charge, traps, and defects at the SiO2/SiC interface. The threshold voltages and blocking performance of MOSFETs are influenced by pre-oxidation nitrogen implantation conditions attributed to changing of counter doping mechanism in the DMOSFET p-well.

Energy-Localized Near-Interface Traps Active in the Strong-Accumulation Region of 4H-SiC MOS Capacitors

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region.

Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.