Mobile Ion Contamination Research Articles

Mobile ions entering the IGBT gate oxide - electrical detection and failure localization by lock-in thermography

Small mobile ions, especially sodium and potassium are known to have the ability to infiltrate and move within gate oxide layers of silicon MOS devices. The ion transport in silicon oxide is either a temperature-driven, isotropic diffusion process, or an electrical ion current in presence of an electric field. Therefore, the high temperature gate bias test with negative polarity provides ideal conditions to identify the presence of mobile ions in the gate oxide of IGBT and MOSFET. Mobile ions in sufficient concentration can severely affect the electric characteristics, such as the turn-on and turn-off behavior of the MOS channel, by creating a shift in the gate threshold voltage or excessive sub-threshold currents. This paper shows several examples of how mobile ions can get into the gate oxide, e.g., via cracks in top side metallization, or by corrosive attack of cap layers. All these different failure modes develop the same electrical failure signature after temperature and/or gate bias stress. During the investigations on mobile ions, a special lock-in thermography method was developed that allows to localize the defect sites in the semiconductor by taking advantage of exclusive excitation of MOS cells affected by mobile ion contamination. Finally, after defect localization, further analytical methods can be applied to identify the exact nature of the access path to the gate oxide. Based on the test and analytical routine described above, a special test method was developed that allows to evaluate the permeability of the semiconductor chip top side structures towards mobile ions and to check for weak spots and potential leakage paths.

Robust Trench Buried-Guard-Ring-Based Termination for Charge Balanced Devices

A major limitation on the performance of high-voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The proposed termination scheme was applied toward a 1350-V fast recovery diode and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after high-temperature reverse bias testing due to mobile ion contamination from packaging mold compound.

Characterization of Electric Field Induced Ion Migration in Semiconductor Encapsulation Materials

: In modern high voltage power semiconductor technologies ion migration is a highly relevant challenge owing to ongoing miniaturization and operation at higher temperatures. Strong electric fields may cause an enrichment of mobile ions in the gate- and field oxide of the transistor which in turn may result in a shift of the threshold or breakdown voltage leading to chip failure. Therefore it is of strong interest to investigate ion migration in modern semiconductor devices. One of the main contamination sources for mobile ions in semiconductor devices is the molding compound used for encapsulation. These materials consist of various substances such as the polymeric matrix, filler materials for mechanical strength, adhesion promoters and flame retardants. In the elaborated production process of these compounds, mobile ion contamination cannot be avoided. Their small ionic radii and their high abundance make sodium, potassium and chlorine the most critical contaminations responsible for mobile ion induced chip failure. The quantitative analysis of concentration and distribution of these impurity ions in modern semiconductor devices is thus urgently needed. A promising analytical technique for measuring the concentration of these ion contaminations is inductive coupled plasma mass spectroscopy (ICP-MS). Experiments show that different ion concentrations were measured with different digestion methods. For instance the sodium content of a commercially available mold compound, measured with a microwave digestion was more than 6 times higher than the same compound measured with a pressure digestion and water extraction. These differences indicate that there are different ion contamination sources within the mold compound with different chemical properties. It seems to be obvious that different chemical properties lead to different field induced ion migration. Therefore it is of great interest to develop an analytical tool allowing the unambiguous measurement of ion migration properties of different mold compounds. Previous publications [1], [2] show techniques to measure ion diffusion in microcircuit encapsulation materials. However, these measurements do not cover electric field induced ion migration. In the present work a measurement setup based on thin film samples with simplified well-defined geometry was used to measure ion migration in encapsulation materials [3]. To that purpose thin samples of standard processed mold compounds were assembled between two silicon wafer electrodes with well-defined silicon dioxide layers between the mold compound and the electrodes. The sample was heated and a bias was applied between the silicon electrodes. Mobile ions moving from the mold compound to the silicon dioxide / silicon interface were monitored by current measurements. The measurement setup is shown in figure 1. After the measurement the mold compound was removed. Time of flight secondary ion mass spectroscopy (TOF-SIMS) depth profiles of the remaining silicon dioxide layers were recorded, which showed that mobile ions such as lithium, sodium potassium and chlorine moved to the silicon dioxide / silicon interface. Due to the fact that only mobile ions were able to penetrate the silicon dioxide layer, identification and quantification of the migrated ions was possible without the influence of the non-migrated ions, which remain in the mold compound. These measurements can be an important tool to compare different mold compounds and evaluate the risk of mobile ion migration. Acknowledgements: This work was jointly funded by the Austrian Research Promotion Agency (FFG, Project No. 846579) and the Carinthian Economic Promotion Fund (KWF, contract KWF-1521/26876/38867).

Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication

Compound semiconductor integration techniques draw ever more attention with increasing demands for high efficiency power electronics, photovoltaic or photonic devices. Aside from methods including epitaxial growth, one of these techniques is direct wafer bonding.An interesting wafer bonding approach for the above-mentioned types of applications would be a process resulting in formation of covalent bonds at room temperature (“covalent bonding”) or at significantly low temperatures (e.g. <100°C). Hence, the common issues arising from bonding of materials with different thermal expansion coefficients could be avoided, in the first place.The challenges in covalent bonding are mostly determined by the rigorous requirements for cleanliness with regards to particle and mobile ion contamination, as well as surface roughness and process uniformity. If the bonding process must produce a conductive interface an intermediate process step needs to be added that reduces/removes the stable native oxides from the substrates surfaces, as they would form an insulating layer in the final bond interface and hence lead to decreased electric device performance. This implies that in addition to the requirements for covalent wafer bonding, an effective and complete oxide removal needs to be guaranteed, to achieve a successful conductive wafer bond. However, as lattice point defects (e.g. interstitials and dislocations) form traps for charge carriers which would affect device performance as well, a suitable oxide removal step would leave the underlying bulk material mostly unchanged. The current work presents preliminary results of a novel technology designed to produce covalent / conductive wafer bonds. Results shown here were obtained in experiments using 200 mm wafers (prime Si and with 300 nm thermally grown oxide) supported by numerical modelling of sub-surface defects using SRIM [1]. The results obtained for Si are used as baseline for the new technology development (equipment and process) before applying it to compound semiconductor-based applications. [1] J. F. Ziegler, M. D. Ziegler, and J. P. Biersack, Nucl. Instrum. Methods Phys. Res. B 268, 1818 (2010).

High-Density Feedthrough Technology for Hermetic Biomedical Micropackaging

ABSTRACTImplantable electronic biomedical devices are used clinically to diagnose and treat an increasing number of medical conditions. Such devices typically employ hermetic packages that often incorporate electrical feedthroughs made with conventional ceramic-to-metal bonding technologies. This sealing technology is well established and provides robust hermetic seals, but is limited in both the number and spacing of electrical leads. Emerging devices for interfacing with the human nervous system, however, will require a large number of external electrical leads implemented in a miniaturized packaging configuration. Commercially available feedthrough technologies are currently incapable of providing external electrical contacts with spacings as small as 200 to 400 microns, and thus are neither compatible with integrated circuit I/O (input/output) pad spacings nor with miniature implantable packages. We report the development of a hermetic high-density feedthrough (HDF) technology that allows for conductive path densities as high as 1,000 per cm2, and that is capable of supporting neural interface devices. The fabrication process utilizes multilayer high temperature co-fired ceramic (HTCC) technology in conjunction with platinum leads. Before co-firing, green alumina substrates are interleaved with linear, parallel Pt trace arrays in either wire or thin foils to form the electrical feedthroughs. Layered stacks of spatially isolated traces are first compacted into a composite, and then fired to achieve densification. After firing, the densified multilayered composite compacts are sliced perpendicular to the Pt traces and lapped to produce multiple feedthrough arrays with a high density of leads (conductors). Both hermeticity and biocompatibility of such implantable feedthroughs are important, as both moisture and positive mobile ion contamination from the saline environment of the human body can lead to compromised performance or catastrophic failure. HDFs fabricated using this process with 100 conductors and lead-to-lead spacings as low as 400 microns have been helium leak tested repeatedly and found to exceed industry-accepted standards with helium leak rates in the range of 10–11 mbar-l/s. The spacing of the current prototype matches industry standard neural interface technology, and can be scaled to higher densities with lead-to-lead spacings as small as 200 microns. The reported HDF process has several distinct advantages over prior approaches, including the provision of a large number of conductive feedthrough leads suitable for flip-chip bonding with sub-mm lead-to-lead spacings (pitch), and the incorporation of materials (alumina and platinum) that are already used in medical implants. The implementation of such an HDF technology allows for significant package miniaturization, allowing greater flexibility in surgical placement as well as less invasive procedures for implantable electronic biomedical devices.

Detection of Mobile Ions in the Presence of Charge Trapping in SiC MOS Devices

Since power devices such as DMOSFETs will operate at high temperature where mobile ion effects are enhanced, identifying their presence is a key reliability issue for power electronics applications. We have detected the presence of mobile ion contamination in some SiC MOS device sample sets and correlated those results with observed high temperature bias instability. The differing behaviors of these devices to bias stressing as a function of temperature suggests that in some cases mobile ion drift may be counteracting the typical charge trapping effect. Triangular voltage sweep (TVS) data indicates the presence of roughly 1-4x1012 cm-2 mobile ions in samples where the bias instability significantly decreased with higher temperature, while samples with a nearly flat or positive-trending response showed overall lower ion contaminations of roughly 6-9x1011 cm-2. These results, although preliminary, support the theory that mobile ion contamination is the cause of negative bias instability at elevated temperatures in SiC MOS.

Modeling the effect of mobile ion contamination on the stability of a microelectromechanical resonator

We present a theoretical model for mobile ion contamination in a silicon microelectromechanical resonator. In the model both drift and diffusion of the mobile charge in dielectric films are taken into account. The model is verified through a comparison to existing experimental data. We show that the model can describe the frequency drift of resonators in a wide temperature range.

Mobile-Ion-Induced Charge Loss Failure in Silicon–Oxide–Nitride–Oxide–Silicon Two-Bit Storage Flash Memory

In silicon–oxide–nitride–oxide–silicon (SONOS) 2-bit storage flash memory, we discovered deterioration of data retention (DR) in the form of charge loss, which is dependent on the distance between contact windows and word lines (WLs) and also on the thermal treatment performed after the formation of contact windows. We hypothesized that the unique structure of the SONOS flash memory leads to susceptibility to mobile ion contamination. We concluded that Na mobile ion contamination originates in the tungsten chemical–mechanical polishing (W-CMP) process, and that the ions diffuse through the boundaries of the boron phosphosilicate glass (BPSG) and stacked oxide–nitride–oxide (ONO) films into the cell area. We successfully reduced the charge loss by cleaning of the contamination source and by the stable control of phosphorus concentration at the bottom of the BPSG. As a permanent countermeasure, we proposed the complete isolation of contact windows from the adjacent ONO layer, and we were able to demonstrate the effectiveness of this proposal.

Stability Enhancement of Polysilicon Thin-Film Transistors Using Stacked Plasma-Enhanced Chemical Vapor Deposited SiO2/SiNx Gate Dielectric

The use of a double-layer, plasma-enhanced chemical vapor deposited SiO2/SiNx film as a gate dielectric material for polysilicon thin-film transistors was investigated in order to reduce mobile ion contamination and to improve gate oxide integrity degradation. We observed that the interposed silicon nitride film between the gate electrode and the SiO2 gate insulator prevents the incorporation of mobile ions into the SiO2 film, and also increases the breakdown voltage of the gate-insulating film. The mobile ion densities for the double SiO2/SiNx and single SiO2 gate dielectrics (no interposed SiNx layer between the gate electrode and SiO2 gate insulator) were 1.3 ×1011 and 1.7 ×1012/cm2, respectively. The breakdown fields at the 50% failure points in the Weibull plots for the double and single dielectric cases were 8 and 5 MV/cm, respectively. We conclude that the silicon nitride layer of the double gate insulator film minimizes ion contamination, leading to the enhancement of breakdown characteristics.

Protection of MOS capacitors during anodic bonding

We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm−1 to 4 × 104 V cm−1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

Optimization of post-CMP cleaning process for elimination of CMP slurry-induced metallic contaminations

We have invetigated the slurry-induced metallic contaminations of undoped and doped silicate oxide surface during the post-chemical mechanical polishing (CMP) cleaning process. The metallic contaminations by CMP slurry were evaluated in the four different oxide films, such as plasma enhanced tetra-ethyl-ortho-silicate glass (PE-TEOS), O3-boro-phospho-silicate glass (O3-BPSG), PE-BPSG, and phospho-silicate glass (PSG). Prior to entering the post-CMP cleaner, all films were polished with KOH-based slurry. The total X-ray fluorescence (TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing, which is due to the CMP slurry. The polished O3 BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS film because of a mobile ion gettering ability of phosphorus. For PSG oxides, the slurry-induced mobile ion contamination increased with an increase of phosphorus content. In addition, the polishing removal rate of PSG oxides had a linear relationship with phosphorus content.

Diffusion Barriers for Mobile Ions in 256M DRAMs

AbstractIn this study, we investigate the diffusion of mobile ions through thin PSG or SiN layers using secondary ion mass spectrometry (SIMS). The diffusivity of Na through either layer is about 100,000X slower than through SiO2. Hence, thin layers of these materials are effective barriers for short anneals at 400°C. However, there is significant diffusion of both Na and K through these layers at 550°C. This suggests that improved cleans will be required to remove mobile ion contamination after interconnect processes.

Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p/sup +/ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO/sub 2/ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950/spl deg/C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO/sub 2/ interface of the p/sup +/ SAS gate capacitor is much smoother than that of the p/sup +/ SAS gate capacitor.

Measurement of Mobile Ion Contamination in Multilayer Metalization by Triangular Voltage Sweep

Advanced complementary metal oxide semiconductor and technologies with complex multilayer metallization (MLM) are increasingly susceptible to mobile ion contamination. The potential of the triangular voltage sweep method (TVS) to provide a useful tool for quantifying mobile ion contamination in product‐like MLM structures was investigated. Sodium was introduced by ion implantation over a practical concentration range into various MLM structures and the resulting concentration was determined by TVS and secondary ion mass spectroscopy (SIMS). Excellent agreement was seen between TVS, SIMS, and implant dose, establishing TVS as a practical tool for monitoring mobile ion contamination in MLM structures. A good correlation between TVS and SIMS was observed not only for implanted sodium but also for contamination introduced by sodium containing solutions, a route more representative of MLM processing. Increased sodium incorporation was observed with the presence of doped oxide under metal‐1. Finally, sodium incorporation was shown to depend directly on the length of metal edge present in the capacitor structure. This suggests that evaluation of simple area capacitors results in an underestimate of mobile ion contamination in circuits.

Plasma versus ozone photoresist ashing: Temperature effects on process-induced mobile ion contamination

Thin gate oxides used in metal-oxide-semiconductor devices are susceptible to mobile ion contamination introduced at critical patterning levels during photoresist stripping. Trace amounts of heavy, alkali metal ions such as sodium (Na+) and potassium (K+) that are found in even the best photoresists are very difficult to oxidize and do not form volatile products that can be easily removed in a typical O2 plasma. These ionic, heavy metals and their byproducts can be driven into critical underlying layers by self-induced bias potentials and positive ion bombardment within an O2 plasma environment. To examine this potential problem, a series of commercially available photoresist ashing systems were selected to study the influence of process-induced mobile ion contamination on sensitive underlying devices. The systems tested included a ‘‘downstream’’ rf plasma asher, a ‘‘downstream’’ microwave plasma system, and a nonplasma ozone ashing system. In this study, photoresist stripping rates and mobile ion (Ni) contamination levels were measured under various processing conditions for 125-, 150-, and 200-mm wafer substrates. Ashing rate measurements are detailed for the ozone ashing system and activation energies are calculated for ozone only and with the addition of nitrous oxide radical products to the ashing gas stream. Measured mobile ion contamination shows a strong temperature dependence for the ‘‘downstream’’ plasma ashing systems tested while the nonplasma, ozone ashing system showed no temperature dependence to process temperatures exceeding 300 °C and it was equal to the wet-chemical controls.

Lateral Diffusion of Na+ Ions from the Gate Edge into the Oxide for P+ and N+ Polycrystalline Silicon Gates

Mobile ion contamination for p+ and n+ polysilicon gates has been studied using the triangular voltage sweep method and secondary ion mass spectroscopy. Mobile ion densities for p+ polysilicon gates are much higher than those for n+ polysilicon gates. Most of Na+ ions in the gate oxide, which are dominant of the mobile ions, diffuse laterally from the gate edge for p+ polysilicon gates but not through the polysilicon. For n+ polysilicon gates, the laterally diffusing Na+ ions are gettered more effectively than those penetrating vertically through the polysilicon.

Refractory metals in submicron IC architecture

Materials traditionally used in integrated circuits have limitations as those circuits reach submicron design rules. Refractory metals have found their place in very-large-scale-integration device technologies, and an experimental program involving the use of tungsten as a gate material has been undertaken, with special emphasis on purity requirements. Bias temperature stress capacitance-voltage measurements show that very low levels of mobile ion contamination can be obtained in metal oxide semiconductor capacitors with tungsten gates sputtered from a special high-purity target.

Gate Oxide Damage in Dry Photoresist Stripping Environments

ABSTRACTThe effect of oxygen plasma stripping environments on the electrical properties of thin oxides has been studied. A barrel, parallel plate and downstream stripper are compared. Damage, measured by shifts in flatband voltage (Δ Vfb), increases in the density of interface traps (Dit), and degradation in minority carrier lifetimes, was observed in all plasma processed samples. Plasma treated wafers had 10–100 fold increases in Dit but recovered to nearly control levels after a 450 °C anneal. ΔVfb and lifetimes did not recover in all cases. Mobile ion contamination dominated in the high temperature (≥ 250 °C) downstream stripping tool. The mobile ion concentration was halved by decreasing the process temperature in the downstream etcher. Ion bombardment-induced damage appears to be most important in the parallel plate configuration. Lifetime results were poor for wafers etched in an unshielded barrel reactor and did not recover after anneal. Use of an etch tunnel improved results to control levels. Degradation of minority carrier lifetimes measured using the photoconductivity technique correlated well with changes in Vfb and Dit. This measurement provides a simple method for evaluating plasma-induced damage.

Fabrication of Highly Reliable Tungsten Gate MOS VLSI's

Recently, refractory metals, such as W and Mo, with low resistivity and a high melting point have received keen interest as materials for gate electrodes and interconnects for MOS VLSI's. However, it is commonly believed that MOS devices with refractory metal gates have low reliability due to mobile ion contamination. In this work, it was clarified that W gates with commercially available W sputtering targets introduced high level mobile charges into the gate oxide. It was also found that the rates of degradation of W gate MOS transistors due to hot carriers were higher than those of poly‐Si gates, and the internal stresses in W gates increased the degradation rates. Therefore, the authors developed a high purity W sputtering target fabrication technique through the use of electron melting. A W gate annealing technique was developed to reduce the internal stress in W films. Through these techniques, the above‐mentioned problems can be eliminated, and W gate devices that have characteristics comparable to those of poly‐Si gates can be produced.

Reduction of Sodium Ion Density in Molybdenum‐Gate MOS Devices with the Addition of Tantalum to Gate Electrodes

The reduction mechanism of mobile ion contamination in Ta‐Mo alloy gate MOS structures has been examined by varying the deposition and annealing conditions of gate metals. Mobile ion density in the gate for the Ta‐Mo gate structures decreases drastically after forming gas annealing at 1000°C, whereas the density increases during nitrogen gas annealing. The structure and composition analysis for the Ta‐Mo gate observed by x‐ray diffraction, SIMS, and AES indicates that nitriding of Ta‐Mo films occurs during the forming gas annealing, and the nitride, (tetragonal, structure), is stable even at 1000°C during annealing. These facts suggest that formation at the boundaries of Mo grains, which is similar to the stuffing effect observed in films, is responsible for immobilizing the sodium atoms within the gate electrodes. As a result, the diffusion of sodium from the gate electrode into the layers is suppressed.