Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication

Abstract

Compound semiconductor integration techniques draw ever more attention with increasing demands for high efficiency power electronics, photovoltaic or photonic devices. Aside from methods including epitaxial growth, one of these techniques is direct wafer bonding.An interesting wafer bonding approach for the above-mentioned types of applications would be a process resulting in formation of covalent bonds at room temperature (“covalent bonding”) or at significantly low temperatures (e.g. <100°C). Hence, the common issues arising from bonding of materials with different thermal expansion coefficients could be avoided, in the first place.The challenges in covalent bonding are mostly determined by the rigorous requirements for cleanliness with regards to particle and mobile ion contamination, as well as surface roughness and process uniformity. If the bonding process must produce a conductive interface an intermediate process step needs to be added that reduces/removes the stable native oxides from the substrates surfaces, as they would form an insulating layer in the final bond interface and hence lead to decreased electric device performance. This implies that in addition to the requirements for covalent wafer bonding, an effective and complete oxide removal needs to be guaranteed, to achieve a successful conductive wafer bond. However, as lattice point defects (e.g. interstitials and dislocations) form traps for charge carriers which would affect device performance as well, a suitable oxide removal step would leave the underlying bulk material mostly unchanged. The current work presents preliminary results of a novel technology designed to produce covalent / conductive wafer bonds. Results shown here were obtained in experiments using 200 mm wafers (prime Si and with 300 nm thermally grown oxide) supported by numerical modelling of sub-surface defects using SRIM [1]. The results obtained for Si are used as baseline for the new technology development (equipment and process) before applying it to compound semiconductor-based applications. [1] J. F. Ziegler, M. D. Ziegler, and J. P. Biersack, Nucl. Instrum. Methods Phys. Res. B 268, 1818 (2010).