Mobile DRAM Research Articles

A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM

This article presents a supply-noise-induced jitter (SIJ) cancellation technique based on an adaptive filter (AF) using a least mean-square (LMS) algorithm. It cancels jitter along with the clock distribution network (CDN) and the transmit paths, which include serializers and pre-drivers. The proposed technique includes a second-order AF to maximize jitter cancellation in the clock path, which has a nonlinear supply-to-jitter characteristic. Implemented in 28-nm CMOS, the proposed SIJ cancellation scheme reduces the rms jitter of the output clock from 27.84 to 4.28 ps and improves the data eye-opening from 22.43 to 104.73 ps when operating at 6.4 Gb/s with a 60-mVPP, 1-MHz supply noise.

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

A time-based (TB) receiver (RX) with a 2-tap TB decision feedback equalizer (DFE) is proposed for mobile DRAM interface. The TB RX consists of a voltage-to-time converter (VTC), a TB DFE, and a time comparator. The VTC converts the RX input voltage to a time difference between two VTC outputs by using the difference in clock-to-Q delays between two latches with different input offset voltages. The TB DFE inserts an additional delay to one of the two VTC outputs and bypasses the other VTC output to increase the time opening. The time comparator makes a decision with the first arriving edge of the two outputs of the TB DFE. While the feedback loop delay must be less than 1 UI for proper operation in the conventional voltage-based DFE, the TB DFE allows the feedback loop delay up to 1.43 UI in this paper. A transmitter (TX) transmits a single-ended signal of 200-mV swing by using an n-over-n voltage-mode driver. The transceiver in a 65-nm CMOS process achieves a 12.5 Gb/s with a 0.8-V supply through a 15-inch FR-4 channel of 14-dB loss. The TX and RX chip consume 4.3 and 3.4 mA, respectively. The energy efficiency is 0.49 pJ/b.

A 2.3-mW 0.01-mm $^{\text{2}}$ 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm2 while consuming 2.27 mW from a 1.0-V supply.

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex></formula> die area.

Fast, exact and non-destructive diagnoses of contact failures in nano-scale semiconductor device using conductive AFM

We fabricated a novel in-line conductive atomic force microscopy (C-AFM), which can analyze the resistive failures and examine process variance with an exact-positioning capability across the whole wafer scale in in-line DRAM fabrication process. Using this in-line C-AFM, we introduced a new, non-destructive diagnosis for resistive failure in mobile DRAM structures. Specially, we focused on the self-aligned contact (SAC) process, because the failure of the SAC process is one of the dominant factors that induces the degradation of yield performance, and is a physically invisible defect. We successfully suggested the accurate pass mark for resistive-failure screening in the fabrication of SAC structures and established that the cause of SAC failures is the bottom silicon oxide layer. Through the accurate pass mark for the SAC process configured by the in-line C-AFM analyses, we secured a good potential method for preventing the yield loss caused by failures in DRAM fabrication.

Stacked 3d package with improved bandwidth and power efficiency

Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhones. The processor ( SoC ) and Mobile DRAM chips are stacked vertically to fit the combination within the restricted board space. The use of wire bonds in the memory chips as well as package level interconnects introduces delays into the data transmitted between the chips and limits the max. clock rate ( at present about 533 MHz for LP DDR 2 memory ) and hence the data transfer rate / bandwidth to less than 6.4 GB per sec. For Smart Phones to become capable of PC quality Games and high speed video would require a doubling of the bandwidth to over 12.8 GB per sec. To achieve that target PoP type packages were to be replaced by 3-d stacks using TSVs and wide I/Os. However recently JEDEC has postponed the introduction of Wide I/O Mobile memory stacks ( using TSVs ) to 2015. So the bandwidth of PoP packages must be improved. A physical way to increase the Bandwidth between the SoC and memory chips in a PoP is by increasing the max. no. of vertical I/Os as this allows more channels / higher parallelism in data transfer. This can be accomplished by shrinking the pitch ( from current 0.4 mm to 0.3 mm ) and doubling the number of rows of vertical I/Os ( from current 2 to 4 ) in PoP. However this requires major effort for the Packaging supply chain and would still fall well short of the future Bandwidth and interconnect Power efficiency targets. In this paper we will describe modifications and additions to the baseline PoP package so that it can be operated at clock rates up to 800 MHz and deliver bandwidth of 12.8 GB per sec or more and match the Interconnect Power efficiency of 3-d stacks with TSVs. Compensation features are introduced for ea. interconnect line between the SoC and Memory in the PoP package. The features are integrated on chips that are inserted between the two layers of the package. The vertical interconnection between the two levels of the PoP are replaced and routed through this additional chip. Only minor changes are required in the baseline PoP package thus will not require long delay to shrink current PoP interconnect pitch etc. The additional chip is built with available technologies and would increase cost by only a fraction of that needed for stacks with TSV-based wide I/O. Simulation results will be presented and compared with test results.

BOOM

To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. This trend creates a new emphasis on high-capacity, high-bandwidth, and high-reliability main memory systems. Conventional and recently-proposed server memory techniques can satisfy these requirements, but at the cost of significantly increased memory power, a key constraint for future memory systems. In this paper, we exploit the low-power nature of another high volume memory component---mobile DRAM---while improving its bandwidth and reliability shortcomings with a new DIMM architecture. We propose Buffered Output On Module (BOOM) that buffers the data outputs from multiple ranks of low-frequency mobile DRAM devices, which in aggregation provide high bandwidth and achieve chipkill-correct or even stronger reliability. Our evaluation shws that BOOM can reduce main memory power by more than 73% relative to the baseline chipkill system, while improving average performance by 5% and providing strong reliability. For memory-intensive applications, BOOM can improve performance by 30--40%.

Towards energy-proportional datacenter memory with mobile DRAM

To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3x the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5x lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

An Energy Efficient $V_{\rm PP}$ Generator With Fast Ramp-Up Time for Mobile DRAM

An energy efficient <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator with fast ramp-up time for mobile DRAM is presented in this paper. Instead of using a fixed pumping clock frequency as in the conventional <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator, the proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator adopts a voltage-controlled oscillator (VCO) and uses variable pumping frequencies to improve the ramp-up time as well as energy efficiency. Numerical results show that the VCO based <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generators achieve energy savings of up to 34% with 40% improvement on ramp-up time when compared to the conventional ring oscillator (RO) based design. Our proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator, which uses a three-stage voltage doubler as a charge pump, was implemented and fabricated in CMOS 0.13 μm process. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator chip's core occupies 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and consumes 1162 nJ (average power of 47.8 mW during 24 μs ramp-up time) while generating 3.0 V output voltage with 1.0 nF load capacitor, 2.0 mA current load and 1.2 V supply voltage.

RF Sensitivity of Multi Chip Package Development by Using Embedded Resistor in Package Substrate

Recently, mobile age is blooming and makes change of 21st century. Especially multi chip package – MCP- is located center position of this flash era. Moreover, radio frequency –RF- sensitivity determines the product quality and life, therefore we try to develop the RF sensitivity of MCP in wireless circumstance. In this study, MCP comprised NAND Flash memory, Mobile DRAM, and a substrate, we focused on the substrate, changed substrate design and performance by using resistor embedded into 1 layer of substrate. The purpose of adaption of embedded resistor is in order to control the slew rate of signal channel of DRAM. NiCr thin film was used for the resistor in substrate. NiCr material presents superior temperature coefficient of resistance –TCR- to thick film material. NiCr coated on Cu foil and this foil laminated by conventional substrate manufacturing method. Embedded resistor applied on signal line as 3 kinds; 1. Signal and signal strobe line by 50 Ohm, 2.Signal strobe line by 50 Ohm, and 3. Signal and signal strobe line by 20 Ohm. In case of 3, result showed 0.5 dBm increment of RF sensitivity in full strength mode, also we got the same performance at half strength mode. Embedded resistor formed substrate did not affect the reliability of MCP, from the results of reliability test; pre-conditioning test, thermo-cyclic, temperature humidity, HAST, un-Bias HAST, and hot temperature storage test. This study showed signal waveform of DRAM is significantly effective in RF sensitivity for MCP. Passive component, resistor, made change of slew rate and revealed increase of sensitivity level finally.

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface

In this paper, a 90° phase-shift delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) is proposed. The proposed DLL increases the accuracies of the duty cycle and 90° phase shift by compensating PVT variation using a closed-loop DCC and a closed-loop 90° phase shift, and achieves a smaller area by reducing the delay-line length by 25% to 50% as compared to conventional DLLs with the DCC and/or 90° phase shift. We also propose a 90° phase detector consisting of a time-to-voltage converter and a sense amplifier to independently control and lock the DCC and 90° phase-shift loops. The proposed DLL is designed using the 0.13 μm process technology with a 1.2 V supply voltage. The operating frequency range is from 400 MHz to 800 MHz. Monte Carlo simulation results show that the output duty cycle error ranges from -0.21% to 0.22% for an input duty cycle range of 30% to 70%, and the 90° phase-shift error is less than 1.66°, which is lower than a 5.7ps error at 800 MHz. Finally, the power consumption of the proposed DLL is 2.8 mW at 800 MHz.

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016mm2 with under 1μW power consumption for providing 0.7°C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

Circuit Design of DRAM for Mobile Generation

In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.

A 1.8 V 128 Mb mobile DRAM with hidden-precharged triple pumping scheme and dual-path hybrid current sense amplifier

A 1.8 V low-voltage and low-power 128 Mb mobile SDRAM is designed and fabricated for hand-held, battery-operated electronic devices with a 0.15-μm CMOS technology. As an essential low-voltage circuit, a triple pumping scheme is proposed to generate a stable boosted voltage whose level exceeds over twice the supply voltage and which is required for the boosted word-line bias. In addition, to convert the bit-line data to a low-voltage CMOS level, a new NMOS and PMOS hybrid folded current sense amplifier with dual-path current sensing scheme is proposed to obtain the stable I -to- V gain as well as to improve the low-voltage margin.

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.